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| author | Jim Lin <jim@andestech.com> | 2025-10-14 08:45:00 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-14 08:45:00 +0800 |
| commit | 1c00a001f605eb87b54d47ce9d7992f7021474b4 (patch) | |
| tree | 1742fc2e7e5de0f230ea5f10d0696fc7ee6b8768 /clang/lib/CIR/CodeGen/CIRGenModule.cpp | |
| parent | 3e22438320003f0c2ed8a8d10b17071d6a093325 (diff) | |
| download | llvm-1c00a001f605eb87b54d47ce9d7992f7021474b4.zip llvm-1c00a001f605eb87b54d47ce9d7992f7021474b4.tar.gz llvm-1c00a001f605eb87b54d47ce9d7992f7021474b4.tar.bz2 | |
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)
That we can merge ADDI with its LHS to ADDIW if its LHS is a
SIGN_EXTEND_INREG.
Diffstat (limited to 'clang/lib/CIR/CodeGen/CIRGenModule.cpp')
0 files changed, 0 insertions, 0 deletions