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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-23 13:18:02 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-23 13:18:02 +0000 |
| commit | ac272635124261c2c4c1f223a27e9dba542343e3 (patch) | |
| tree | ae84a5c3c42e1ed7fd92645db2f2b29ea7f2ac0d /clang/lib/Basic/VirtualFileSystem.cpp | |
| parent | 3a01af08053ba914876b51d116136538dbcc5b95 (diff) | |
| download | llvm-ac272635124261c2c4c1f223a27e9dba542343e3.zip llvm-ac272635124261c2c4c1f223a27e9dba542343e3.tar.gz llvm-ac272635124261c2c4c1f223a27e9dba542343e3.tar.bz2 | |
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6
Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.
MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.
mips64-load-store-left-right.ll has been merged into load-store-left-right.ll
The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3872
llvm-svn: 209512
Diffstat (limited to 'clang/lib/Basic/VirtualFileSystem.cpp')
0 files changed, 0 insertions, 0 deletions