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authorCarolineConcatto <caroline.concatto@arm.com>2024-05-17 09:25:21 +0100
committerGitHub <noreply@github.com>2024-05-17 09:25:21 +0100
commitc4bac7f7dcd931a5e561604e95656a24c3d1c9d9 (patch)
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[LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (#77665)
…VE2.1 for spill/fill When possible the spill/fill register in Frame Lowering uses the ld/st consecutive pairs available in sme or sve2.1.
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