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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-02 08:45:33 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-02 09:12:40 -0800 |
| commit | 7142ec3aaf55f22e9de69fc15bba61cee9b694e0 (patch) | |
| tree | be3c8f8271b3788b8d833ca3e541d80d026fac80 /clang/lib/Basic/Module.cpp | |
| parent | 55f15f99cbb33ce39fa44b6d2c90eef7ad9a376d (diff) | |
| download | llvm-7142ec3aaf55f22e9de69fc15bba61cee9b694e0.zip llvm-7142ec3aaf55f22e9de69fc15bba61cee9b694e0.tar.gz llvm-7142ec3aaf55f22e9de69fc15bba61cee9b694e0.tar.bz2 | |
[RISCV] When matching RORIW, make sure the same input is given to both shifts.
The code is looking for (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))).
We need to ensure X and Y are the same.
Differential Revision: https://reviews.llvm.org/D90580
Diffstat (limited to 'clang/lib/Basic/Module.cpp')
0 files changed, 0 insertions, 0 deletions