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| author | Michael Maitland <michaeltmaitland@gmail.com> | 2023-06-21 14:40:41 -0700 |
|---|---|---|
| committer | Michael Maitland <michaeltmaitland@gmail.com> | 2023-06-22 10:15:17 -0700 |
| commit | ecef87b2a2675fa86e06f88b69b3f98b7822aedc (patch) | |
| tree | 74347d98a8b67721d728571f59ed231a9cabc5fc /clang/lib/Basic/IdentifierTable.cpp | |
| parent | 578d229a1a49bbb0c74a33ceb4b2e087735787cc (diff) | |
| download | llvm-ecef87b2a2675fa86e06f88b69b3f98b7822aedc.zip llvm-ecef87b2a2675fa86e06f88b69b3f98b7822aedc.tar.gz llvm-ecef87b2a2675fa86e06f88b69b3f98b7822aedc.tar.bz2 | |
[RISCV] Improve SiFive7 for loads and stores
* Unit-stride loads and stores can operate at the full bandwidth of the
memory pipe. The memory pipe is DLEN bits wide.
* Strided loads and stores operate at one element per cycle and should
be scheduled accordingly.
* Indexed loads and stores operate at one element per cycle, and they
stall the machine until all addresses have been generated, so they
cannot be scheduled.
* Unit stride seg2 load is number of DLEN parts
* seg3-8 are one segment per cycle, unless the segment is larger
than DLEN in which each segment takes multiple cycles.
Differential Revision: https://reviews.llvm.org/D153475
Diffstat (limited to 'clang/lib/Basic/IdentifierTable.cpp')
0 files changed, 0 insertions, 0 deletions