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| author | Mallikarjuna Gouda <mgouda@mips.com> | 2025-04-29 13:06:27 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-29 03:36:27 -0400 |
| commit | ffcca5112b653b35cafc68a01e654dcdc5a84ff4 (patch) | |
| tree | b34af1ce7ffa5f47323de0de2636b3dd4de5f3d2 /clang/lib/AST/ByteCode/Program.cpp | |
| parent | ff66d34286b07ba864029776d097e66306cc53ef (diff) | |
| download | llvm-ffcca5112b653b35cafc68a01e654dcdc5a84ff4.zip llvm-ffcca5112b653b35cafc68a01e654dcdc5a84ff4.tar.gz llvm-ffcca5112b653b35cafc68a01e654dcdc5a84ff4.tar.bz2 | |
[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (#132704)
Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6
processor.
i6400 and i6500 share same instruction latencies.
CPU has following pipelines
- Two ALUs
- Multiply and Divide unit (MDU)
- Branch Unit (CTU)
- Load/Store Unit (LSU)
- Short Floating-point Unit and
- Long Floating-point Unit
Latency information is available at:
https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions