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| author | Craig Topper <craig.topper@sifive.com> | 2025-10-20 17:17:00 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-21 00:17:00 +0000 |
| commit | e32f08f4e45f4c39dcd029b32dc0ed3673357656 (patch) | |
| tree | a64c28ef1bab48ec044c737d15ff61b51f8985c4 /clang/lib/AST/ByteCode/Program.cpp | |
| parent | f3805fc187705a322a07ed832f153c442d00d495 (diff) | |
| download | llvm-e32f08f4e45f4c39dcd029b32dc0ed3673357656.zip llvm-e32f08f4e45f4c39dcd029b32dc0ed3673357656.tar.gz llvm-e32f08f4e45f4c39dcd029b32dc0ed3673357656.tar.bz2 | |
[RISCV] Use shiftMaskXLen for one of the BCLR patterns. (#164206)
This allows us to remove AND from the shift amount when DAG combine
has replaced (not (shl 1, X)) with (rotl -2, X). SimplifyDemandedBits
will often simplify the rotl case on its own, but not if the masked
shift amount has multiple users.
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions