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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-08-19 11:14:14 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-19 11:14:14 +0530 |
| commit | c00b04a7e041bcf0aaf92cf9aacfe536458f1911 (patch) | |
| tree | 76d7ed3a6abbc7e23de46e98e1db5ca5214fb358 /clang/lib/AST/ByteCode/Program.cpp | |
| parent | 6f7c77fe900ec41b75ca1b9f43355ad8e3e170d7 (diff) | |
| download | llvm-c00b04a7e041bcf0aaf92cf9aacfe536458f1911.zip llvm-c00b04a7e041bcf0aaf92cf9aacfe536458f1911.tar.gz llvm-c00b04a7e041bcf0aaf92cf9aacfe536458f1911.tar.bz2 | |
[RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)
Generate QC_INSB/QC_INSBI from `or (and X, MaskImm), OrImm` iff the
value being inserted only sets known zero bits. This is based on a
similar DAG to DAG transform done in `AArch64`.
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions