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| author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2025-08-27 09:12:49 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-27 09:12:49 +0100 |
| commit | 818b39ef64e780127ecbaace0c0b27b351b5f987 (patch) | |
| tree | af0507045127db2ca98d01aa991ec9761df3375f /clang/lib/AST/ByteCode/Compiler.cpp | |
| parent | 88f8ab01b5855bbd7375b7a3d83d9a78d77f3fdf (diff) | |
| download | llvm-818b39ef64e780127ecbaace0c0b27b351b5f987.zip llvm-818b39ef64e780127ecbaace0c0b27b351b5f987.tar.gz llvm-818b39ef64e780127ecbaace0c0b27b351b5f987.tar.bz2 | |
[AArch64][SME] Simplify initialization of the TPIDR2 block (#141049)
This patch updates the definition of `AArch64ISD::INIT_TPIDR2OBJ` to
take the number of save slices (which is currently always all ZA
slices). Using this, we can initialize the TPIDR2 block with a single
STP of the save buffer pointer and the number of save slices. The
reserved bytes (10-15) will be implicitly zeroed as the result of RDSVL
will always be <= 16-bits.
Note: We used to write the number of save slices to the TPIDR2 block
before every call with a lazy save; however, based on 6.6.9 "Changes to
the TPIDR2 block" in the aapcs64
(https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#changes-to-the-tpidr2-block),
it seems we can rely on callers preserving the contents of the TPIDR2 block.
Diffstat (limited to 'clang/lib/AST/ByteCode/Compiler.cpp')
0 files changed, 0 insertions, 0 deletions