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| author | Tiger Ding <38360323+zerogtiger@users.noreply.github.com> | 2025-08-18 11:04:27 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-19 00:04:27 +0900 |
| commit | 4ab14685a0b96b48f8fd77ead55c1816668cac18 (patch) | |
| tree | 6de9aa371d40451da2a56ced151f171b298d1cc1 /clang/lib/AST/ByteCode/Compiler.cpp | |
| parent | 7c53c6162bd43d952546a3ef7d019babd5244c29 (diff) | |
| download | llvm-4ab14685a0b96b48f8fd77ead55c1816668cac18.zip llvm-4ab14685a0b96b48f8fd77ead55c1816668cac18.tar.gz llvm-4ab14685a0b96b48f8fd77ead55c1816668cac18.tar.bz2 | |
[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)
Lowering in GlobalISel for AMDGPU previously always narrows to i32 on
truncating store regardless of mem size or scalar size, causing issues
with types like i65 which is first extended to i128 then stored as i64 +
i8 to i128 locations. Narrowing only on store to pow of 2 mem location
ensures only narrowing to mem size near end of legalization.
This LLVM defect was identified via the AMD Fuzzing project.
Diffstat (limited to 'clang/lib/AST/ByteCode/Compiler.cpp')
0 files changed, 0 insertions, 0 deletions