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| author | Jianjian Guan <jacquesguan@me.com> | 2025-09-19 14:30:48 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-19 14:30:48 +0800 |
| commit | 332eb5f693d2e28026aaa4f580cef607898ed756 (patch) | |
| tree | ddb959a8dc1f01a4aef023ee9108c1dbe58e9414 /clang/lib/AST/ByteCode/Compiler.cpp | |
| parent | dd669c32ec67c1a995134339657ace2a2047c605 (diff) | |
| download | llvm-332eb5f693d2e28026aaa4f580cef607898ed756.zip llvm-332eb5f693d2e28026aaa4f580cef607898ed756.tar.gz llvm-332eb5f693d2e28026aaa4f580cef607898ed756.tar.bz2 | |
[RISCV][GISel] Support select vx, vf form rvv intrinsics (#157398)
For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank.
Diffstat (limited to 'clang/lib/AST/ByteCode/Compiler.cpp')
0 files changed, 0 insertions, 0 deletions