diff options
| author | Jay Foad <jay.foad@amd.com> | 2022-04-26 16:29:06 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2022-04-26 16:29:26 +0100 |
| commit | fb571719d5c9bd2b7f09695f7242cdf09850b9ae (patch) | |
| tree | f9ebf984d96b9e008b69ef195242f503566f5db1 | |
| parent | 69c66bb211228d4969caa64fba462c321bc3438c (diff) | |
| download | llvm-fb571719d5c9bd2b7f09695f7242cdf09850b9ae.zip llvm-fb571719d5c9bd2b7f09695f7242cdf09850b9ae.tar.gz llvm-fb571719d5c9bd2b7f09695f7242cdf09850b9ae.tar.bz2 | |
[TableGen] Dump RC.AllocationPriority with -register-info-debug
| -rw-r--r-- | llvm/utils/TableGen/RegisterInfoEmitter.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index cafe233..8696cbb 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1726,6 +1726,7 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) { OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; OS << "\tAllocatable: " << RC.Allocatable << '\n'; + OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; OS << "\tRegs:"; for (const CodeGenRegister *R : RC.getMembers()) { OS << " " << R->getName(); |