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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-09-09 16:58:52 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-09-09 19:45:40 -0400 |
| commit | e15215e04154e1bc8ea57d46f36b054adf49a3ed (patch) | |
| tree | 643918d05e23310e5c82482090d4173e09ea5456 | |
| parent | 85490874b23ba1337210dbcb700b258ffb751b78 (diff) | |
| download | llvm-e15215e04154e1bc8ea57d46f36b054adf49a3ed.zip llvm-e15215e04154e1bc8ea57d46f36b054adf49a3ed.tar.gz llvm-e15215e04154e1bc8ea57d46f36b054adf49a3ed.tar.bz2 | |
AMDGPU: Hoist check for VGPRs
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 5abe392..ae1f6e2 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -1026,8 +1026,10 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore( continue; RegInterval Interval = ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I); + + const bool IsVGPR = TRI->isVGPR(*MRI, Op.getReg()); for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo) { - if (TRI->isVGPR(*MRI, Op.getReg())) { + if (IsVGPR) { // RAW always needs an s_waitcnt. WAW needs an s_waitcnt unless the // previous write and this write are the same type of VMEM // instruction, in which case they're guaranteed to write their |