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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-11-07 20:50:01 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-07 20:50:01 -0800 |
| commit | de4aa9cdeab07c9a7cb94be0e09929ae67374998 (patch) | |
| tree | 7b96fe4f7df0c4ce629ccafe5cb11c62e69e1fd6 | |
| parent | 2a3ef056fdd9ecff21282d1865d50e1c4708cdc1 (diff) | |
| download | llvm-de4aa9cdeab07c9a7cb94be0e09929ae67374998.zip llvm-de4aa9cdeab07c9a7cb94be0e09929ae67374998.tar.gz llvm-de4aa9cdeab07c9a7cb94be0e09929ae67374998.tar.bz2 | |
AMDGPU: Minor SDWA pass cleanups (#166629)
Don't use low level regclass query in SDWA pass.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index bfac639..caff354 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -1334,20 +1334,21 @@ void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, const MCInstrDesc &Desc = TII->get(MI.getOpcode()); unsigned ConstantBusCount = 0; for (MachineOperand &Op : MI.explicit_uses()) { - if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) - continue; - - unsigned I = Op.getOperandNo(); + if (Op.isReg()) { + if (TRI->isVGPR(*MRI, Op.getReg())) + continue; - int16_t RegClass = TII->getOpRegClassID(Desc.operands()[I]); - if (RegClass == -1 || !TRI->isVSSuperClass(TRI->getRegClass(RegClass))) + if (ST.hasSDWAScalar() && ConstantBusCount == 0) { + ++ConstantBusCount; + continue; + } + } else if (!Op.isImm()) continue; - if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() && - TRI->isSGPRReg(*MRI, Op.getReg())) { - ++ConstantBusCount; + unsigned I = Op.getOperandNo(); + const TargetRegisterClass *OpRC = TII->getRegClass(Desc, I, TRI); + if (!OpRC || !TRI->isVSSuperClass(OpRC)) continue; - } Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); auto Copy = BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(), |