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| author | Jessica Paquette <jpaquette@apple.com> | 2019-02-09 00:37:31 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-02-09 00:37:31 +0000 |
| commit | c230c13d4bcbca85ba50ee0f7df123245d65a615 (patch) | |
| tree | d50e5d15964caee9343bebfb4040c1f3f3bd7994 | |
| parent | 1607a37308cc6993f86ccef1122bb3daab327d5d (diff) | |
| download | llvm-c230c13d4bcbca85ba50ee0f7df123245d65a615.zip llvm-c230c13d4bcbca85ba50ee0f7df123245d65a615.tar.gz llvm-c230c13d4bcbca85ba50ee0f7df123245d65a615.tar.bz2 | |
Recommit "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR""
After r353586, we won't fail on the AMDGPU floor pattern that was killing the
importer before.
llvm-svn: 353589
4 files changed, 15 insertions, 1 deletions
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index f44f0f1..70a2128 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -530,6 +530,9 @@ HANDLE_TARGET_OPCODE(G_FSIN) /// Floating point square root. HANDLE_TARGET_OPCODE(G_FSQRT) +/// Floating point floor. +HANDLE_TARGET_OPCODE(G_FFLOOR) + /// Generic AddressSpaceCast. HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index b61ed92..41d1ed9 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -579,6 +579,13 @@ def G_FSQRT : GenericInstruction { let hasSideEffects = 0; } +// Floating point floor of a value. +def G_FFLOOR : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + //------------------------------------------------------------------------------ // Opcodes for LLVM Intrinsics //------------------------------------------------------------------------------ diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index cbda4ab..6b0434a 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -93,6 +93,7 @@ def : GINodeEquiv<G_FCOS, fcos>; def : GINodeEquiv<G_FSIN, fsin>; def : GINodeEquiv<G_FABS, fabs>; def : GINodeEquiv<G_FSQRT, fsqrt>; +def : GINodeEquiv<G_FFLOOR, ffloor>; // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some // complications that tablegen must take care of. For example, Predicates such diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 09574f0..ab144ee 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -340,7 +340,10 @@ # DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. the first uncovered type index: 1, OK +# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index +# DEBUG: .. type index coverage check SKIPPED: no rules defined # CHECK-NOT: ill-defined |