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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-04-12 23:57:30 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-04-12 23:57:30 +0000 |
| commit | 703b2ec43fd707342b0e5e110c2348bb8cfbd4c3 (patch) | |
| tree | fec763d8289a181837525d25790c87a2f0ced20c | |
| parent | 818f67add508ebe478a313dfa4a02bcab224a130 (diff) | |
| download | llvm-703b2ec43fd707342b0e5e110c2348bb8cfbd4c3.zip llvm-703b2ec43fd707342b0e5e110c2348bb8cfbd4c3.tar.gz llvm-703b2ec43fd707342b0e5e110c2348bb8cfbd4c3.tar.bz2 | |
AMDGPU/SI: Fix spilling of 96-bit registers
Summary:
It seems like this was broken in r252327. I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.
Reviewers: arsenm, nhaehnle
Subscribers: nhaehnle, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19021
llvm-svn: 266152
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index ef5b3db..01a8054 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -551,6 +551,8 @@ static unsigned getVGPRSpillSaveOpcode(unsigned Size) { return AMDGPU::SI_SPILL_V32_SAVE; case 8: return AMDGPU::SI_SPILL_V64_SAVE; + case 12: + return AMDGPU::SI_SPILL_V96_SAVE; case 16: return AMDGPU::SI_SPILL_V128_SAVE; case 32: @@ -642,6 +644,8 @@ static unsigned getVGPRSpillRestoreOpcode(unsigned Size) { return AMDGPU::SI_SPILL_V32_RESTORE; case 8: return AMDGPU::SI_SPILL_V64_RESTORE; + case 12: + return AMDGPU::SI_SPILL_V96_RESTORE; case 16: return AMDGPU::SI_SPILL_V128_RESTORE; case 32: |