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| author | Chris Lattner <sabre@nondot.org> | 2005-04-19 05:41:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-19 05:41:52 +0000 |
| commit | 53c40624f9bf5d71fbd50331b1bcffb0d535f33b (patch) | |
| tree | 2c488d2f1b53395276a7bb519729b6bafc87e19d | |
| parent | baa9be572b8a2545be4d3eecbb9486fca9129b29 (diff) | |
| download | llvm-53c40624f9bf5d71fbd50331b1bcffb0d535f33b.zip llvm-53c40624f9bf5d71fbd50331b1bcffb0d535f33b.tar.gz llvm-53c40624f9bf5d71fbd50331b1bcffb0d535f33b.tar.bz2 | |
Add completely untested support for mtcrf/mfcrf encoding
llvm-svn: 21353
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp index 57b92b4..574e21e 100644 --- a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp @@ -186,6 +186,13 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { // or things that get fixed up later by the JIT. if (MO.isRegister()) { rv = enumRegToMachineReg(MO.getReg()); + + // Special encoding for MTCRF and MFCRF, which uses a bit mask for the + // register, not the register number directly. + if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFCRF) && + (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) { + rv = 0x80 >> rv; + } } else if (MO.isImmediate()) { rv = MO.getImmedValue(); } else if (MO.isGlobalAddress() || MO.isExternalSymbol()) { |