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| author | Craig Topper <craig.topper@intel.com> | 2020-08-09 20:24:54 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-08-09 20:24:56 -0700 |
| commit | 1675f8a2516d0a6f90744aef1066482ee072bbc8 (patch) | |
| tree | 516e8e406dea596c3155fc51f779aaecf3d3020f | |
| parent | a31b3893c72d7f30b05fc42a26690a331ca7b6ed (diff) | |
| download | llvm-1675f8a2516d0a6f90744aef1066482ee072bbc8.zip llvm-1675f8a2516d0a6f90744aef1066482ee072bbc8.tar.gz llvm-1675f8a2516d0a6f90744aef1066482ee072bbc8.tar.bz2 | |
[TableGen] Pull the increment of a variable out of an assert.
The variable is only used by the assert so the code was fine
before, but it was flagged in PR47072.
| -rw-r--r-- | llvm/utils/TableGen/RegisterInfoEmitter.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index a615587..b30a8b3 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1288,7 +1288,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << CGH.getMode(M).Name; OS << ")\n"; for (const auto &RC : RegisterClasses) { - assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); + assert(RC.EnumValue == EV && "Unexpected order of register classes"); + ++EV; (void)EV; const RegSizeInfo &RI = RC.RSI.get(M); OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " |