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path: root/sysdeps/x86/dl-cacheinfo.h
AgeCommit message (Expand)AuthorFilesLines
2024-08-26x86: Enable non-temporal memset for Hygon processorsFeifei Wang1-1/+1
2024-08-26x86: Add cache information support for Hygon processorsFeifei Wang1-0/+60
2024-08-15x86: Add `Avoid_STOSB` tunable to allow NT memset without ERMSNoah Goldstein1-5/+29
2024-08-15x86: Use `Avoid_Non_Temporal_Memset` to control non-temporal pathNoah Goldstein1-8/+7
2024-07-16x86: Disable non-temporal memset on Skylake ServerNoah Goldstein1-7/+8
2024-06-30x86: Set default non_temporal_threshold for Zhaoxin processorsMayShao-oc1-2/+4
2024-06-14x86: Fix value for `x86_memset_non_temporal_threshold` when it is undesirableNoah Goldstein1-3/+3
2024-06-10x86: Enable non-temporal memset tunable for AMDJoe Damato1-4/+4
2024-05-30x86: Add seperate non-temporal tunable for memsetNoah Goldstein1-0/+16
2024-02-13x86: Do not prefer ERMS for memset on Zen3+Adhemerval Zanella1-0/+5
2024-02-13x86: Fix Zen3/Zen4 ERMS selection (BZ 30994)Adhemerval Zanella1-20/+18
2024-01-01Update copyright dates with scripts/update-copyrightsPaul Eggert1-1/+1
2023-08-29x86: Check the lower byte of EAX of CPUID leaf 2 [BZ #30643]H.J. Lu1-18/+13
2023-08-11x86: Fix incorrect scope of setting `shared_per_thread` [BZ# 30745]Noah Goldstein1-4/+3
2023-08-06x86: Fix for cache computation on AMD legacy cpus.Sajan Karumanchi1-27/+199
2023-07-18[PATCH v1] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold.Noah Goldstein1-3/+12
2023-07-18x86: Fix slight bug in `shared_per_thread` cache size calculation.Noah Goldstein1-2/+2
2023-06-19Fix misspellings -- BZ 25337Paul Pluzhnikov1-1/+1
2023-06-12x86: Make the divisor in setting `non_temporal_threshold` cpu specificNoah Goldstein1-13/+19
2023-06-12x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4`Noah Goldstein1-27/+43
2023-05-27x86: Use 64MB as nt-store threshold if no cacheinfo [BZ #30429]Noah Goldstein1-1/+9
2023-04-04x86/dl-cacheinfo: remove unsused parameter from handle_amdAndreas Schwab1-36/+30
2023-03-29Remove --enable-tunables configure optionAdhemerval Zanella Netto1-10/+0
2023-01-18x86: Cache computation for AMD architecture.Sajan Karumanchi1-159/+45
2023-01-06Update copyright dates with scripts/update-copyrightsJoseph Myers1-1/+1
2023-01-03x86: Check minimum/maximum of non_temporal_threshold [BZ #29953]H.J. Lu1-9/+16
2022-06-15x86: Add bounds `x86_non_temporal_threshold`Noah Goldstein1-1/+7
2022-06-14x86: Fix misordered logic for setting `rep_movsb_stop_threshold`Noah Goldstein1-12/+12
2022-01-01Update copyright dates with scripts/update-copyrightsPaul Eggert1-1/+1
2021-11-06x86: Double size of ERMS rep_movsb_threshold in dl-cacheinfo.hNoah Goldstein1-3/+5
2021-05-03x86: Set rep_movsb_threshold to 2112 on processors with FSRMH.J. Lu1-0/+4
2021-03-15x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]H.J. Lu1-0/+6
2021-02-10x86: Use SIZE_MAX instead of (long int)-1 for tunable range valueSiddhesh Poyarekar1-5/+5
2021-02-10tunables: Simplify TUNABLE_SET interfaceSiddhesh Poyarekar1-9/+6
2021-02-02x86: Adding an upper bound for Enhanced REP MOVSB.Sajan Karumanchi1-1/+14
2021-01-21<sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu1-2/+2
2021-01-14x86: Move x86 processor cache info to cpu_featuresH.J. Lu1-0/+460
2021-01-02Update copyright dates with scripts/update-copyrightsPaul Eggert1-1/+1
2020-10-16x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu1-0/+478
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