diff options
Diffstat (limited to 'sysdeps')
41 files changed, 380 insertions, 159 deletions
diff --git a/sysdeps/aarch64/multiarch/memcpy_oryon1.S b/sysdeps/aarch64/multiarch/memcpy_oryon1.S index e86d8b0..cc267db 100644 --- a/sysdeps/aarch64/multiarch/memcpy_oryon1.S +++ b/sysdeps/aarch64/multiarch/memcpy_oryon1.S @@ -152,6 +152,46 @@ L(copy96): .p2align 6 L(copy_long): + /* On oryon1 cores, large memcpy's are helped by using ldnp/stnp. + This loop is identical to the one below it but using ldnp/stnp + instructions. For loops that are less than 32768 bytes, + the ldnp/stnp instructions will not help and will cause a slow + down so only use the ldnp/stnp loop for the largest sizes. */ + + cmp count, #32768 + b.lo L(copy_long_without_nontemp) + and tmp1, dstin, 15 + bic dst, dstin, 15 + ldnp D_l, D_h, [src] + sub src, src, tmp1 + add count, count, tmp1 /* Count is now 16 too large. */ + ldnp A_l, A_h, [src, 16] + stnp D_l, D_h, [dstin] + ldnp B_l, B_h, [src, 32] + ldnp C_l, C_h, [src, 48] + ldnp D_l, D_h, [src, 64] + add src, src, #64 + subs count, count, 128 + 16 /* Test and readjust count. */ + +L(nontemp_loop64): + tbz src, #6, 1f +1: + stnp A_l, A_h, [dst, 16] + ldnp A_l, A_h, [src, 16] + stnp B_l, B_h, [dst, 32] + ldnp B_l, B_h, [src, 32] + stnp C_l, C_h, [dst, 48] + ldnp C_l, C_h, [src, 48] + stnp D_l, D_h, [dst, 64] + ldnp D_l, D_h, [src, 64] + add src, src, #64 + add dst, dst, #64 + subs count, count, 64 + b.hi L(nontemp_loop64) + b L(last64) + +L(copy_long_without_nontemp): + and tmp1, dstin, 15 bic dst, dstin, 15 ldp D_l, D_h, [src] diff --git a/sysdeps/aarch64/multiarch/memset_oryon1.S b/sysdeps/aarch64/multiarch/memset_oryon1.S index 0f9b718..88f4ef4 100644 --- a/sysdeps/aarch64/multiarch/memset_oryon1.S +++ b/sysdeps/aarch64/multiarch/memset_oryon1.S @@ -90,6 +90,8 @@ L(set_long): cmp count, 256 ccmp valw, 0, 0, cs b.eq L(try_zva) + cmp count, #32768 + b.hi L(set_long_with_nontemp) /* Small-size or non-zero memset does not use DC ZVA. */ sub count, dstend, dst @@ -112,6 +114,30 @@ L(set_long): stp val, val, [dstend, -16] ret +L(set_long_with_nontemp): + /* Small-size or non-zero memset does not use DC ZVA. */ + sub count, dstend, dst + + /* Adjust count and bias for loop. By subtracting extra 1 from count, + it is easy to use tbz instruction to check whether loop tailing + count is less than 33 bytes, so as to bypass 2 unnecessary stps. */ + sub count, count, 64+16+1 + +1: stnp val, val, [dst, 16] + stnp val, val, [dst, 32] + stnp val, val, [dst, 48] + stnp val, val, [dst, 64] + add dst, dst, #64 + subs count, count, 64 + b.hs 1b + + tbz count, 5, 1f /* Remaining count is less than 33 bytes? */ + stnp val, val, [dst, 16] + stnp val, val, [dst, 32] +1: stnp val, val, [dstend, -32] + stnp val, val, [dstend, -16] + ret + L(try_zva): /* Write the first and last 64 byte aligned block using stp rather than using DC ZVA as it is faster. */ diff --git a/sysdeps/generic/ldsodefs.h b/sysdeps/generic/ldsodefs.h index 5b12a41..b5d5b31 100644 --- a/sysdeps/generic/ldsodefs.h +++ b/sysdeps/generic/ldsodefs.h @@ -717,6 +717,19 @@ extern const ElfW(Phdr) *_dl_phdr; extern size_t _dl_phnum; #endif +/* Possible values for the glibc.rtld.execstack tunable. */ +enum stack_tunable_mode + { + /* Do not allow executable stacks, even if program requires it. */ + stack_tunable_mode_disable = 0, + /* Follows either ABI requirement, or the PT_GNU_STACK value. */ + stack_tunable_mode_enable = 1, + /* Always enable an executable stack. */ + stack_tunable_mode_force = 2 + }; + +void _dl_handle_execstack_tunable (void) attribute_hidden; + /* This function changes the permission of the memory region pointed by STACK_ENDP to executable and update the internal memory protection flags for future thread stack creation. */ diff --git a/sysdeps/ieee754/ldbl-128/e_expl.c b/sysdeps/ieee754/ldbl-128/e_expl.c index 25b45c7..4855c6b 100644 --- a/sysdeps/ieee754/ldbl-128/e_expl.c +++ b/sysdeps/ieee754/ldbl-128/e_expl.c @@ -79,7 +79,7 @@ L(-11433.4627433362978788372438434526231), /* 3x2^96 */ #define THREEp96 C[2] - L(59421121885698253195157962752.0), + L(237684487542793012780631851008.0), /* 3x2^103 */ #define THREEp103 C[3] diff --git a/sysdeps/mach/hurd/i386/libc.abilist b/sysdeps/mach/hurd/i386/libc.abilist index 0b963dc..3e183f5 100644 --- a/sysdeps/mach/hurd/i386/libc.abilist +++ b/sysdeps/mach/hurd/i386/libc.abilist @@ -2614,6 +2614,10 @@ GLIBC_2.42 pthread_rwlockattr_destroy F GLIBC_2.42 pthread_rwlockattr_getpshared F GLIBC_2.42 pthread_rwlockattr_init F GLIBC_2.42 pthread_rwlockattr_setpshared F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/mach/hurd/x86_64/libc.abilist b/sysdeps/mach/hurd/x86_64/libc.abilist index b9e9349..688ee26 100644 --- a/sysdeps/mach/hurd/x86_64/libc.abilist +++ b/sysdeps/mach/hurd/x86_64/libc.abilist @@ -2297,6 +2297,10 @@ GLIBC_2.42 pthread_rwlockattr_destroy F GLIBC_2.42 pthread_rwlockattr_getpshared F GLIBC_2.42 pthread_rwlockattr_init F GLIBC_2.42 pthread_rwlockattr_setpshared F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F HURD_CTHREADS_0.3 __cthread_getspecific F HURD_CTHREADS_0.3 __cthread_keycreate F HURD_CTHREADS_0.3 __cthread_setspecific F diff --git a/sysdeps/powerpc/powerpc64/dl-machine.h b/sysdeps/powerpc/powerpc64/dl-machine.h index d8d7c8b..89e26bb 100644 --- a/sysdeps/powerpc/powerpc64/dl-machine.h +++ b/sysdeps/powerpc/powerpc64/dl-machine.h @@ -363,7 +363,6 @@ elf_machine_runtime_setup (struct link_map *map, struct r_scope_elem *scope[], / sizeof (Elf64_Rela)); Elf64_Addr l_addr = map->l_addr; Elf64_Dyn **info = map->l_info; - char *p; extern void _dl_runtime_resolve (void); extern void _dl_profile_resolve (void); @@ -435,20 +434,6 @@ elf_machine_runtime_setup (struct link_map *map, struct r_scope_elem *scope[], offset += PLT_ENTRY_WORDS; glink_offset += GLINK_ENTRY_WORDS (i); } - - /* Now, we've modified data. We need to write the changes from - the data cache to a second-level unified cache, then make - sure that stale data in the instruction cache is removed. - (In a multiprocessor system, the effect is more complex.) - Most of the PLT shouldn't be in the instruction cache, but - there may be a little overlap at the start and the end. - - Assumes that dcbst and icbi apply to lines of 16 bytes or - more. Current known line sizes are 16, 32, and 128 bytes. */ - - for (p = (char *) plt; p < (char *) &plt[offset]; p += 16) - PPC_DCBST (p); - PPC_SYNC; } } return lazy; diff --git a/sysdeps/pthread/tst-stdio2.c b/sysdeps/pthread/tst-stdio2.c index 08948cb..0876ed6 100644 --- a/sysdeps/pthread/tst-stdio2.c +++ b/sysdeps/pthread/tst-stdio2.c @@ -75,7 +75,7 @@ do_test (void) exit (1); } - puts ("join returned succsefully"); + puts ("join returned successfully"); return 0; } diff --git a/sysdeps/unix/sysv/linux/aarch64/libc.abilist b/sysdeps/unix/sysv/linux/aarch64/libc.abilist index 41f8f39..aa6bf48 100644 --- a/sysdeps/unix/sysv/linux/aarch64/libc.abilist +++ b/sysdeps/unix/sysv/linux/aarch64/libc.abilist @@ -2753,3 +2753,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/alpha/libc.abilist b/sysdeps/unix/sysv/linux/alpha/libc.abilist index 34efc96..d5df965 100644 --- a/sysdeps/unix/sysv/linux/alpha/libc.abilist +++ b/sysdeps/unix/sysv/linux/alpha/libc.abilist @@ -3100,6 +3100,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/arc/libc.abilist b/sysdeps/unix/sysv/linux/arc/libc.abilist index de7c618..c46c08d 100644 --- a/sysdeps/unix/sysv/linux/arc/libc.abilist +++ b/sysdeps/unix/sysv/linux/arc/libc.abilist @@ -2514,3 +2514,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/arm/be/libc.abilist b/sysdeps/unix/sysv/linux/arm/be/libc.abilist index 96f0314..4df150c 100644 --- a/sysdeps/unix/sysv/linux/arm/be/libc.abilist +++ b/sysdeps/unix/sysv/linux/arm/be/libc.abilist @@ -2806,6 +2806,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/arm/le/libc.abilist b/sysdeps/unix/sysv/linux/arm/le/libc.abilist index 635468f..be29478 100644 --- a/sysdeps/unix/sysv/linux/arm/le/libc.abilist +++ b/sysdeps/unix/sysv/linux/arm/le/libc.abilist @@ -2803,6 +2803,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/csky/libc.abilist b/sysdeps/unix/sysv/linux/csky/libc.abilist index 490694d..f123757 100644 --- a/sysdeps/unix/sysv/linux/csky/libc.abilist +++ b/sysdeps/unix/sysv/linux/csky/libc.abilist @@ -2790,3 +2790,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/hppa/libc.abilist b/sysdeps/unix/sysv/linux/hppa/libc.abilist index b1905da..2dc85b9 100644 --- a/sysdeps/unix/sysv/linux/hppa/libc.abilist +++ b/sysdeps/unix/sysv/linux/hppa/libc.abilist @@ -2827,6 +2827,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/i386/libc.abilist b/sysdeps/unix/sysv/linux/i386/libc.abilist index 424ef34..1e38217 100644 --- a/sysdeps/unix/sysv/linux/i386/libc.abilist +++ b/sysdeps/unix/sysv/linux/i386/libc.abilist @@ -3010,6 +3010,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/loongarch/lp64/libc.abilist b/sysdeps/unix/sysv/linux/loongarch/lp64/libc.abilist index 420471e..927fc21 100644 --- a/sysdeps/unix/sysv/linux/loongarch/lp64/libc.abilist +++ b/sysdeps/unix/sysv/linux/loongarch/lp64/libc.abilist @@ -2274,3 +2274,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist b/sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist index 95a68c7..74da49d 100644 --- a/sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist +++ b/sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist @@ -2786,6 +2786,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist b/sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist index 442e82b..e5d6781 100644 --- a/sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist +++ b/sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist @@ -2953,6 +2953,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/microblaze/be/libc.abilist b/sysdeps/unix/sysv/linux/microblaze/be/libc.abilist index 20f7712..4dbd4b6 100644 --- a/sysdeps/unix/sysv/linux/microblaze/be/libc.abilist +++ b/sysdeps/unix/sysv/linux/microblaze/be/libc.abilist @@ -2839,3 +2839,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/microblaze/le/libc.abilist b/sysdeps/unix/sysv/linux/microblaze/le/libc.abilist index f61ed3b..c5965bb 100644 --- a/sysdeps/unix/sysv/linux/microblaze/le/libc.abilist +++ b/sysdeps/unix/sysv/linux/microblaze/le/libc.abilist @@ -2836,3 +2836,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist b/sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist index 381120c..10715e0 100644 --- a/sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist +++ b/sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist @@ -2914,6 +2914,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist b/sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist index 2f51146..3d229b9 100644 --- a/sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist +++ b/sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist @@ -2912,6 +2912,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist b/sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist index e6071be..e4cb452 100644 --- a/sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist +++ b/sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist @@ -2920,6 +2920,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist b/sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist index f41e209..8a32d25 100644 --- a/sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist +++ b/sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist @@ -2822,6 +2822,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/or1k/libc.abilist b/sysdeps/unix/sysv/linux/or1k/libc.abilist index bbcdb31..64dac95 100644 --- a/sysdeps/unix/sysv/linux/or1k/libc.abilist +++ b/sysdeps/unix/sysv/linux/or1k/libc.abilist @@ -2264,3 +2264,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist b/sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist index e0ea22b..cc5e93c 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist @@ -3143,6 +3143,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist b/sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist index 16b9a77..9814997 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist @@ -3188,6 +3188,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/be/libc.abilist b/sysdeps/unix/sysv/linux/powerpc/powerpc64/be/libc.abilist index 070f6f5..7f46295 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/be/libc.abilist +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/be/libc.abilist @@ -2897,6 +2897,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/le/libc.abilist b/sysdeps/unix/sysv/linux/powerpc/powerpc64/le/libc.abilist index 4378d1d..f24f81b 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/le/libc.abilist +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/le/libc.abilist @@ -2973,3 +2973,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/riscv/rv32/libc.abilist b/sysdeps/unix/sysv/linux/riscv/rv32/libc.abilist index 48c6e26..9330c7a 100644 --- a/sysdeps/unix/sysv/linux/riscv/rv32/libc.abilist +++ b/sysdeps/unix/sysv/linux/riscv/rv32/libc.abilist @@ -2517,3 +2517,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/riscv/rv64/libc.abilist b/sysdeps/unix/sysv/linux/riscv/rv64/libc.abilist index a8b0c6a..ea4555d 100644 --- a/sysdeps/unix/sysv/linux/riscv/rv64/libc.abilist +++ b/sysdeps/unix/sysv/linux/riscv/rv64/libc.abilist @@ -2717,3 +2717,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist b/sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist index 6c00b84..3e625fa 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist +++ b/sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist @@ -3141,6 +3141,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist b/sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist index f866e5d..46b4a04 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist +++ b/sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist @@ -2934,6 +2934,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/sh/be/libc.abilist b/sysdeps/unix/sysv/linux/sh/be/libc.abilist index 4f2db8c..36a94c9 100644 --- a/sysdeps/unix/sysv/linux/sh/be/libc.abilist +++ b/sysdeps/unix/sysv/linux/sh/be/libc.abilist @@ -2833,6 +2833,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/sh/le/libc.abilist b/sysdeps/unix/sysv/linux/sh/le/libc.abilist index a73473e..f79aba6 100644 --- a/sysdeps/unix/sysv/linux/sh/le/libc.abilist +++ b/sysdeps/unix/sysv/linux/sh/le/libc.abilist @@ -2830,6 +2830,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist b/sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist index dc7e27d..4a6acc0 100644 --- a/sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist +++ b/sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist @@ -3162,6 +3162,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist b/sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist index 2ee97f4..931109d 100644 --- a/sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist +++ b/sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist @@ -2798,6 +2798,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/x86_64/64/libc.abilist b/sysdeps/unix/sysv/linux/x86_64/64/libc.abilist index a7ada1e..7ab9073 100644 --- a/sysdeps/unix/sysv/linux/x86_64/64/libc.abilist +++ b/sysdeps/unix/sysv/linux/x86_64/64/libc.abilist @@ -2749,6 +2749,10 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F GLIBC_2.5 __readlinkat_chk F GLIBC_2.5 inet6_opt_append F GLIBC_2.5 inet6_opt_find F diff --git a/sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist b/sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist index f41ab77..e11876f 100644 --- a/sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist +++ b/sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist @@ -2768,3 +2768,7 @@ GLIBC_2.41 sched_setattr F GLIBC_2.42 __inet_ntop_chk F GLIBC_2.42 __inet_pton_chk F GLIBC_2.42 pthread_gettid_np F +GLIBC_2.42 uabs F +GLIBC_2.42 uimaxabs F +GLIBC_2.42 ulabs F +GLIBC_2.42 ullabs F diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 9d136e4..e50f1d6 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -502,8 +502,8 @@ _Static_assert (((index_arch_Fast_Unaligned_Load "Incorrect index_arch_Fast_Unaligned_Load"); -/* Intel Family-6 microarch list. */ -enum +/* Intel microarch list. */ +enum intel_microarch { /* Atom processors. */ INTEL_ATOM_BONNELL, @@ -512,6 +512,7 @@ enum INTEL_ATOM_GOLDMONT, INTEL_ATOM_GOLDMONT_PLUS, INTEL_ATOM_SIERRAFOREST, + INTEL_ATOM_CLEARWATERFOREST, INTEL_ATOM_GRANDRIDGE, INTEL_ATOM_TREMONT, @@ -539,7 +540,9 @@ enum INTEL_BIGCORE_METEORLAKE, INTEL_BIGCORE_LUNARLAKE, INTEL_BIGCORE_ARROWLAKE, + INTEL_BIGCORE_PANTHERLAKE, INTEL_BIGCORE_GRANITERAPIDS, + INTEL_BIGCORE_DIAMONDRAPIDS, /* Mixed (bigcore + atom SOC). */ INTEL_MIXED_LAKEFIELD, @@ -553,7 +556,7 @@ enum INTEL_UNKNOWN, }; -static unsigned int +static enum intel_microarch intel_get_fam6_microarch (unsigned int model, __attribute__ ((unused)) unsigned int stepping) { @@ -584,6 +587,8 @@ intel_get_fam6_microarch (unsigned int model, return INTEL_ATOM_GOLDMONT_PLUS; case 0xAF: return INTEL_ATOM_SIERRAFOREST; + case 0xDD: + return INTEL_ATOM_CLEARWATERFOREST; case 0xB6: return INTEL_ATOM_GRANDRIDGE; case 0x86: @@ -691,8 +696,12 @@ intel_get_fam6_microarch (unsigned int model, return INTEL_BIGCORE_METEORLAKE; case 0xbd: return INTEL_BIGCORE_LUNARLAKE; + case 0xb5: + case 0xc5: case 0xc6: return INTEL_BIGCORE_ARROWLAKE; + case 0xCC: + return INTEL_BIGCORE_PANTHERLAKE; case 0xAD: case 0xAE: return INTEL_BIGCORE_GRANITERAPIDS; @@ -756,133 +765,20 @@ init_cpu_features (struct cpu_features *cpu_features) cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] &= ~bit_arch_Avoid_Non_Temporal_Memset; + enum intel_microarch microarch = INTEL_UNKNOWN; if (family == 0x06) { model += extended_model; - unsigned int microarch - = intel_get_fam6_microarch (model, stepping); + microarch = intel_get_fam6_microarch (model, stepping); + /* Disable TSX on some processors to avoid TSX on kernels that + weren't updated with the latest microcode package (which + disables broken feature by default). */ switch (microarch) { - /* Atom / KNL tuning. */ - case INTEL_ATOM_BONNELL: - /* BSF is slow on Bonnell. */ - cpu_features->preferred[index_arch_Slow_BSF] - |= bit_arch_Slow_BSF; - break; - - /* Unaligned load versions are faster than SSSE3 - on Airmont, Silvermont, Goldmont, and Goldmont Plus. */ - case INTEL_ATOM_AIRMONT: - case INTEL_ATOM_SILVERMONT: - case INTEL_ATOM_GOLDMONT: - case INTEL_ATOM_GOLDMONT_PLUS: - - /* Knights Landing. Enable Silvermont optimizations. */ - case INTEL_KNIGHTS_LANDING: - - cpu_features->preferred[index_arch_Fast_Unaligned_Load] - |= (bit_arch_Fast_Unaligned_Load - | bit_arch_Fast_Unaligned_Copy - | bit_arch_Prefer_PMINUB_for_stringop - | bit_arch_Slow_SSE4_2); - break; - - case INTEL_ATOM_TREMONT: - /* Enable rep string instructions, unaligned load, unaligned - copy, pminub and avoid SSE 4.2 on Tremont. */ - cpu_features->preferred[index_arch_Fast_Rep_String] - |= (bit_arch_Fast_Rep_String - | bit_arch_Fast_Unaligned_Load - | bit_arch_Fast_Unaligned_Copy - | bit_arch_Prefer_PMINUB_for_stringop - | bit_arch_Slow_SSE4_2); - break; - - /* - Default tuned Knights microarch. - case INTEL_KNIGHTS_MILL: - */ - - /* - Default tuned atom microarch. - case INTEL_ATOM_SIERRAFOREST: - case INTEL_ATOM_GRANDRIDGE: - */ - - /* Bigcore/Default Tuning. */ default: - default_tuning: - /* Unknown family 0x06 processors. Assuming this is one - of Core i3/i5/i7 processors if AVX is available. */ - if (!CPU_FEATURES_CPU_P (cpu_features, AVX)) - break; - - enable_modern_features: - /* Rep string instructions, unaligned load, unaligned copy, - and pminub are fast on Intel Core i3, i5 and i7. */ - cpu_features->preferred[index_arch_Fast_Rep_String] - |= (bit_arch_Fast_Rep_String - | bit_arch_Fast_Unaligned_Load - | bit_arch_Fast_Unaligned_Copy - | bit_arch_Prefer_PMINUB_for_stringop); break; - case INTEL_BIGCORE_NEHALEM: - case INTEL_BIGCORE_WESTMERE: - /* Older CPUs prefer non-temporal stores at lower threshold. */ - cpu_features->cachesize_non_temporal_divisor = 8; - goto enable_modern_features; - - /* Older Bigcore microarch (smaller non-temporal store - threshold). */ - case INTEL_BIGCORE_SANDYBRIDGE: - case INTEL_BIGCORE_IVYBRIDGE: - case INTEL_BIGCORE_HASWELL: - case INTEL_BIGCORE_BROADWELL: - cpu_features->cachesize_non_temporal_divisor = 8; - goto default_tuning; - - /* Newer Bigcore microarch (larger non-temporal store - threshold). */ - case INTEL_BIGCORE_SKYLAKE_AVX512: - case INTEL_BIGCORE_CANNONLAKE: - /* Benchmarks indicate non-temporal memset is not - necessarily profitable on SKX (and in some cases much - worse). This is likely unique to SKX due its it unique - mesh interconnect (not present on ICX or BWD). Disable - non-temporal on all Skylake servers. */ - cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] - |= bit_arch_Avoid_Non_Temporal_Memset; - /* fallthrough */ - case INTEL_BIGCORE_COMETLAKE: - case INTEL_BIGCORE_SKYLAKE: - case INTEL_BIGCORE_KABYLAKE: - case INTEL_BIGCORE_ICELAKE: - case INTEL_BIGCORE_TIGERLAKE: - case INTEL_BIGCORE_ROCKETLAKE: - case INTEL_BIGCORE_RAPTORLAKE: - case INTEL_BIGCORE_METEORLAKE: - case INTEL_BIGCORE_LUNARLAKE: - case INTEL_BIGCORE_ARROWLAKE: - case INTEL_BIGCORE_SAPPHIRERAPIDS: - case INTEL_BIGCORE_EMERALDRAPIDS: - case INTEL_BIGCORE_GRANITERAPIDS: - cpu_features->cachesize_non_temporal_divisor = 2; - goto default_tuning; - - /* Default tuned Mixed (bigcore + atom SOC). */ - case INTEL_MIXED_LAKEFIELD: - case INTEL_MIXED_ALDERLAKE: - cpu_features->cachesize_non_temporal_divisor = 2; - goto default_tuning; - } - - /* Disable TSX on some processors to avoid TSX on kernels that - weren't updated with the latest microcode package (which - disables broken feature by default). */ - switch (microarch) - { case INTEL_BIGCORE_SKYLAKE_AVX512: /* 0x55 (Skylake-avx512) && stepping <= 5 disable TSX. */ if (stepping <= 5) @@ -891,38 +787,163 @@ init_cpu_features (struct cpu_features *cpu_features) case INTEL_BIGCORE_KABYLAKE: /* NB: Although the errata documents that for model == 0x8e - (kabylake skylake client), only 0xb stepping or lower are - impacted, the intention of the errata was to disable TSX on - all client processors on all steppings. Include 0xc - stepping which is an Intel Core i7-8665U, a client mobile - processor. */ + (kabylake skylake client), only 0xb stepping or lower are + impacted, the intention of the errata was to disable TSX on + all client processors on all steppings. Include 0xc + stepping which is an Intel Core i7-8665U, a client mobile + processor. */ if (stepping > 0xc) break; /* Fall through. */ case INTEL_BIGCORE_SKYLAKE: - /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for - processors listed in: - -https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html - */ - disable_tsx: - CPU_FEATURE_UNSET (cpu_features, HLE); - CPU_FEATURE_UNSET (cpu_features, RTM); - CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); - break; + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for + processors listed in: + + https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html + */ +disable_tsx: + CPU_FEATURE_UNSET (cpu_features, HLE); + CPU_FEATURE_UNSET (cpu_features, RTM); + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); + break; case INTEL_BIGCORE_HASWELL: - /* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working - TSX. Haswell also include other model numbers that have - working TSX. */ - if (model == 0x3f && stepping >= 4) + /* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working + TSX. Haswell also includes other model numbers that have + working TSX. */ + if (model == 0x3f && stepping >= 4) break; - CPU_FEATURE_UNSET (cpu_features, RTM); - break; + CPU_FEATURE_UNSET (cpu_features, RTM); + break; } } + else if (family == 19) + switch (model) + { + case 0x01: + microarch = INTEL_BIGCORE_DIAMONDRAPIDS; + break; + default: + break; + } + + switch (microarch) + { + /* Atom / KNL tuning. */ + case INTEL_ATOM_BONNELL: + /* BSF is slow on Bonnell. */ + cpu_features->preferred[index_arch_Slow_BSF] + |= bit_arch_Slow_BSF; + break; + + /* Unaligned load versions are faster than SSSE3 + on Airmont, Silvermont, Goldmont, and Goldmont Plus. */ + case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: + + /* Knights Landing. Enable Silvermont optimizations. */ + case INTEL_KNIGHTS_LANDING: + + cpu_features->preferred[index_arch_Fast_Unaligned_Load] + |= (bit_arch_Fast_Unaligned_Load + | bit_arch_Fast_Unaligned_Copy + | bit_arch_Prefer_PMINUB_for_stringop + | bit_arch_Slow_SSE4_2); + break; + + case INTEL_ATOM_TREMONT: + /* Enable rep string instructions, unaligned load, unaligned + copy, pminub and avoid SSE 4.2 on Tremont. */ + cpu_features->preferred[index_arch_Fast_Rep_String] + |= (bit_arch_Fast_Rep_String + | bit_arch_Fast_Unaligned_Load + | bit_arch_Fast_Unaligned_Copy + | bit_arch_Prefer_PMINUB_for_stringop + | bit_arch_Slow_SSE4_2); + break; + + /* + Default tuned Knights microarch. + case INTEL_KNIGHTS_MILL: + */ + + /* + Default tuned atom microarch. + case INTEL_ATOM_SIERRAFOREST: + case INTEL_ATOM_GRANDRIDGE: + case INTEL_ATOM_CLEARWATERFOREST: + */ + + /* Bigcore/Default Tuning. */ + default: + default_tuning: + /* Unknown Intel processors. Assuming this is one of Core + i3/i5/i7 processors if AVX is available. */ + if (!CPU_FEATURES_CPU_P (cpu_features, AVX)) + break; + + enable_modern_features: + /* Rep string instructions, unaligned load, unaligned copy, + and pminub are fast on Intel Core i3, i5 and i7. */ + cpu_features->preferred[index_arch_Fast_Rep_String] + |= (bit_arch_Fast_Rep_String + | bit_arch_Fast_Unaligned_Load + | bit_arch_Fast_Unaligned_Copy + | bit_arch_Prefer_PMINUB_for_stringop); + break; + + case INTEL_BIGCORE_NEHALEM: + case INTEL_BIGCORE_WESTMERE: + /* Older CPUs prefer non-temporal stores at lower threshold. */ + cpu_features->cachesize_non_temporal_divisor = 8; + goto enable_modern_features; + + /* Older Bigcore microarch (smaller non-temporal store + threshold). */ + case INTEL_BIGCORE_SANDYBRIDGE: + case INTEL_BIGCORE_IVYBRIDGE: + case INTEL_BIGCORE_HASWELL: + case INTEL_BIGCORE_BROADWELL: + cpu_features->cachesize_non_temporal_divisor = 8; + goto default_tuning; + + /* Newer Bigcore microarch (larger non-temporal store + threshold). */ + case INTEL_BIGCORE_SKYLAKE_AVX512: + case INTEL_BIGCORE_CANNONLAKE: + /* Benchmarks indicate non-temporal memset is not + necessarily profitable on SKX (and in some cases much + worse). This is likely unique to SKX due to its unique + mesh interconnect (not present on ICX or BWD). Disable + non-temporal on all Skylake servers. */ + cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] + |= bit_arch_Avoid_Non_Temporal_Memset; + /* fallthrough */ + case INTEL_BIGCORE_COMETLAKE: + case INTEL_BIGCORE_SKYLAKE: + case INTEL_BIGCORE_KABYLAKE: + case INTEL_BIGCORE_ICELAKE: + case INTEL_BIGCORE_TIGERLAKE: + case INTEL_BIGCORE_ROCKETLAKE: + case INTEL_BIGCORE_RAPTORLAKE: + case INTEL_BIGCORE_METEORLAKE: + case INTEL_BIGCORE_LUNARLAKE: + case INTEL_BIGCORE_ARROWLAKE: + case INTEL_BIGCORE_PANTHERLAKE: + case INTEL_BIGCORE_SAPPHIRERAPIDS: + case INTEL_BIGCORE_EMERALDRAPIDS: + case INTEL_BIGCORE_GRANITERAPIDS: + case INTEL_BIGCORE_DIAMONDRAPIDS: + /* Default tuned Mixed (bigcore + atom SOC). */ + case INTEL_MIXED_LAKEFIELD: + case INTEL_MIXED_ALDERLAKE: + cpu_features->cachesize_non_temporal_divisor = 2; + goto default_tuning; + } /* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER if AVX512ER is available. Don't use AVX512 to avoid lower CPU |