diff options
| author | Ulrich Drepper <drepper@redhat.com> | 2007-10-10 01:22:45 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2007-10-10 01:22:45 +0000 |
| commit | 5a01ab7b838c967ba38720136a71d8b89d5b79ce (patch) | |
| tree | 7418c83a84b06fcca931dca2569e5f456431220b /sysdeps | |
| parent | 7753717472f38aa44d636ade701f3a948d275ff3 (diff) | |
| download | glibc-5a01ab7b838c967ba38720136a71d8b89d5b79ce.zip glibc-5a01ab7b838c967ba38720136a71d8b89d5b79ce.tar.gz glibc-5a01ab7b838c967ba38720136a71d8b89d5b79ce.tar.bz2 | |
* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problem
with some Pentium Ds.
Diffstat (limited to 'sysdeps')
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index 5b92bd5..12102fe 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -456,6 +456,13 @@ init_cacheinfo (void) asm volatile ("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "0" (4), "2" (i++)); + + /* There seems to be a bug in at least some Pentium Ds + which sometimes fail to iterate all cache parameters. + Do not loop indefinitely here, stop in this case and + assume there is no such information. */ + if ((eax & 0x1f) == 0) + goto intel_bug_no_cache_info; } while (((eax >> 5) & 0x7) != level); @@ -463,6 +470,7 @@ init_cacheinfo (void) } else { + intel_bug_no_cache_info: /* Assume that all logical threads share the highest cache level. */ asm volatile ("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) |