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| author | Zong Li <zongbox@gmail.com> | 2018-11-30 17:18:20 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-27 08:17:43 -0700 |
| commit | 2ed993ada6fc29c0589d4818595df200e1d93a16 (patch) | |
| tree | 78de36190978acd6965dba58616e180856fd3759 /sysdeps/unix/sysv/linux/riscv/configure | |
| parent | b2d175cdb755277ef5579fdac914768003bfbc5c (diff) | |
| download | glibc-2ed993ada6fc29c0589d4818595df200e1d93a16.zip glibc-2ed993ada6fc29c0589d4818595df200e1d93a16.tar.gz glibc-2ed993ada6fc29c0589d4818595df200e1d93a16.tar.bz2 | |
RISC-V: Fix llrint and llround missing exceptions on RV32
Conversions from a float to a long long on 32-bit RISC-V (RV32) may not
raise the correct exceptions on overflow, it also may raise spurious
"inexact" exceptions on non overflow cases. This patch fixes the
problem, similarly to the fix for MIPS, ARM and S390.
Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
Diffstat (limited to 'sysdeps/unix/sysv/linux/riscv/configure')
0 files changed, 0 insertions, 0 deletions