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| author | Hongbo Zhang <hongbo.zhang@linaro.org> | 2018-06-12 21:29:11 +0530 |
|---|---|---|
| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2018-06-12 21:29:11 +0530 |
| commit | fc2ba8037dec486c0557eba0b807060ace857701 (patch) | |
| tree | 07932c664817a919bd56a432cd59af8cff38096b /sysdeps/unix/sysv/linux/aarch64/cpu-features.h | |
| parent | 5aad5f617892e75d91d4c8fb7594ff35b610c042 (diff) | |
| download | glibc-fc2ba8037dec486c0557eba0b807060ace857701.zip glibc-fc2ba8037dec486c0557eba0b807060ace857701.tar.gz glibc-fc2ba8037dec486c0557eba0b807060ace857701.tar.bz2 | |
aarch64: add HXT Phecda core memory operation ifuncs
Phecda is HXT semiconductor's CPU core, this patch adds memory operation
ifuncs for it: sharing the same optimized implementation with Qualcomm's
Falkor core.
2018-06-07 Minfeng Kang <minfeng.kang@hxt-semitech.com>
Hongbo Zhang <hongbo.zhang@linaro.org>
* sysdeps/aarch64/multiarch/memcpy.c (libc_ifunc): reuse
__memcpy_falkor for phecda core.
* sysdeps/aarch64/multiarch/memmove.c (libc_ifunc): reuse
__memmove_falkor for phecda core.
* sysdeps/aarch64/multiarch/memset.c (libc_ifunc): reuse
__memset_falkor for phecda core.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.c: add MIDR entry
for phecda core.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_PHECDA): add
macro to identify phecda core.
Diffstat (limited to 'sysdeps/unix/sysv/linux/aarch64/cpu-features.h')
| -rw-r--r-- | sysdeps/unix/sysv/linux/aarch64/cpu-features.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index cde655b..eb35adf 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -49,6 +49,9 @@ #define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \ && MIDR_PARTNUM(midr) == 0xc00) +#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ + && MIDR_PARTNUM(midr) == 0x000) + struct cpu_features { uint64_t midr_el1; |