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| author | Aurelien Jarno <aurelien@aurel32.net> | 2022-01-17 19:41:40 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2022-01-17 19:42:46 +0100 |
| commit | c242fcce06e3102ca663b2f992611d0bda4f2668 (patch) | |
| tree | 5d5a8daef9019c06ce60bf7aea819fdc97de42bb /mathvec | |
| parent | 9702a41cee31e3588e46485a5db06d1d7c222d30 (diff) | |
| download | glibc-c242fcce06e3102ca663b2f992611d0bda4f2668.zip glibc-c242fcce06e3102ca663b2f992611d0bda4f2668.tar.gz glibc-c242fcce06e3102ca663b2f992611d0bda4f2668.tar.bz2 | |
x86: use default cache size if it cannot be determined [BZ #28784]
In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can
not be retrieved and the corresponding values are set to 0.
Commit 2d651eb9265d ("x86: Move x86 processor cache info to
cpu_features") changed the behaviour in such case by defining the
__x86_shared_cache_size and __x86_data_cache_size variables to 0 instead
of using the default values. This cause an issue with the i686 SSE2
optimized bzero/routine which assumes that the cache size is at least
128 bytes, and otherwise tries to zero/set the whole address space minus
128 bytes.
Fix that by restoring the original code to only update
__x86_shared_cache_size and __x86_data_cache_size variables if the
corresponding cache sizes are not zero.
Fixes bug 28784
Fixes commit 2d651eb9265d
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Diffstat (limited to 'mathvec')
0 files changed, 0 insertions, 0 deletions