[powerpc] fe{en,dis}ableexcept, fesetmode: optimize FPSCR accesses

Since fe{en,dis}ableexcept() and fesetmode() read-modify-write just the
"mode" (exception enable and rounding mode) bits of the Floating Point Status
Control Register (FPSCR), the lighter weight 'mffsl' instruction can be used
to read the FPSCR (enables and rounding mode), and 'mtfsf 0b00000011' can be
used to write just those bits back to the FPSCR.  The net is better performance.

In addition, fe{en,dis}ableexcept() read the FPSCR again after writing it, or
they determine that it doesn't need to be written because it is not changing.
In either case, the local variable holds the current values of the enable
bits in the FPSCR.  This local variable can be used instead of again reading
the FPSCR.

Also, that value of the FPSCR which is read the second time is validated
against the requested enables.  Since the write can't fail, this validation
step is unnecessary, and can be removed.  Instead, the exceptions to be
enabled (or disabled) are transformed into available bits in the FPSCR,
then validated after being transformed back, to ensure that all requested
bits are actually being set.  For example, FE_INVALID_SQRT can be
requested, but cannot actually be set.  This bit is not mapped during the
transformations, so a test for that bit being set before and after
transformations will show the bit would not be set, and the function will
return -1 for failure.

Finally, convert the local macros in fesetmode.c to more generally useful
macros in fenv_libc.h.

1 files changed, 11 insertions, 0 deletions

diff --git a/ChangeLog b/ChangeLog
index c2d7071..1609d16 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,16 @@
 2019-08-28  Paul A. Clarke  <pc@us.ibm.com>
     
+    	* sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): New.
+    	(FPSCR_FPRF_MASK): New. (FPSCR_STATUS_MASK): New.
+    	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Use lighter-
+    	weight access to FPSCR; remove unnecessary second FPSCR read and
+    	validate.
+    	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
+    	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Use lighter-weight
+    	access to FPSCR; Use macros in fenv_libc.h in favor of local.
+
+2019-08-28  Paul A. Clarke  <pc@us.ibm.com>
+    
     	* sysdeps/powerpc/fpu/fenv_libc.h: Define FPSCR bitmasks.
     	(fenv_reg_to_exceptions): Replace bitwise operations with mask-shift.
     	(fenv_exceptions_to_reg): New.