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authorH.J. Lu <hjl.tools@gmail.com>2017-08-14 05:54:25 -0700
committerH.J. Lu <hjl.tools@gmail.com>2017-08-14 05:54:38 -0700
commit73322d5ff6ad71c65f875095c4801771cff9ab2d (patch)
tree6dfe6b618b2501adfed46076a4d06cc3b4b0b5e0
parentdbc303ef76503793b4744004984d248346602479 (diff)
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x86: Add IBT/SHSTK bits to cpu-features
Add IBT/SHSTK bits to cpu-features for Shadow Stack in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf * sysdeps/x86/cpu-features.h (bit_cpu_BIT): New. (bit_cpu_SHSTK): Likewise. (index_cpu_IBT): Likewise. (index_cpu_SHSTK): Likewise. (reg_IBT): Likewise. (reg_SHSTK): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Handle index_cpu_IBT and index_cpu_SHSTK.
-rw-r--r--ChangeLog11
-rw-r--r--sysdeps/x86/cpu-features.h8
-rw-r--r--sysdeps/x86/cpu-tunables.c2
3 files changed, 21 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog
index 4067862..7527943 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,14 @@
+2017-08-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * sysdeps/x86/cpu-features.h (bit_cpu_BIT): New.
+ (bit_cpu_SHSTK): Likewise.
+ (index_cpu_IBT): Likewise.
+ (index_cpu_SHSTK): Likewise.
+ (reg_IBT): Likewise.
+ (reg_SHSTK): Likewise.
+ * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)):
+ Handle index_cpu_IBT and index_cpu_SHSTK.
+
2017-08-14 Mike FABIAN <mfabian@redhat.com>
[BZ #19982]
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index af52689..9733e6e 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -74,6 +74,8 @@
#define bit_cpu_AVX512CD (1 << 28)
#define bit_cpu_AVX512BW (1 << 30)
#define bit_cpu_AVX512VL (1u << 31)
+#define bit_cpu_IBT (1u << 20)
+#define bit_cpu_SHSTK (1u << 7)
/* XCR0 Feature flags. */
#define bit_XMM_state (1 << 1)
@@ -103,6 +105,8 @@
# define index_cpu_AVX2 COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET
# define index_cpu_ERMS COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET
# define index_cpu_MOVBE COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
+# define index_cpu_IBT COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EDX_OFFSET
+# define index_cpu_SHSTK COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_ECX_OFFSET
# define index_arch_Fast_Rep_String FEATURE_INDEX_1*FEATURE_SIZE
# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1*FEATURE_SIZE
@@ -220,6 +224,8 @@ extern const struct cpu_features *__get_cpu_features (void)
# define index_cpu_LZCNT COMMON_CPUID_INDEX_1
# define index_cpu_MOVBE COMMON_CPUID_INDEX_1
# define index_cpu_POPCNT COMMON_CPUID_INDEX_1
+# define index_cpu_IBT COMMON_CPUID_INDEX_7
+# define index_cpu_SHSTK COMMON_CPUID_INDEX_7
# define reg_CX8 edx
# define reg_CMOV edx
@@ -249,6 +255,8 @@ extern const struct cpu_features *__get_cpu_features (void)
# define reg_LZCNT ecx
# define reg_MOVBE ecx
# define reg_POPCNT ecx
+# define reg_IBT edx
+# define reg_SHSTK ecx
# define index_arch_Fast_Rep_String FEATURE_INDEX_1
# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1
diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c
index 872dd12..0ab708c 100644
--- a/sysdeps/x86/cpu-tunables.c
+++ b/sysdeps/x86/cpu-tunables.c
@@ -164,6 +164,7 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp)
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, CX8, 3);
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, FMA, 3);
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, HTT, 3);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, IBT, 3);
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, RTM, 3);
}
break;
@@ -186,6 +187,7 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp)
{
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, LZCNT, 5);
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, MOVBE, 5);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SHSTK, 5);
CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSSE3, 5);
}
break;