aboutsummaryrefslogtreecommitdiff
path: root/sim/testsuite/d10v-elf/t-rte.s
blob: 5ce31ddbf41a367f6000fd6b7cce2713850ac485 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
.include "t-macros.i"

	start

	PSW_BITS = PSW_C|PSW_F0|PSW_F1
	
	ldi	r6, #success@word
	mvtc	r6, bpc
	ldi	r6, #PSW_BITS
	mvtc	r6, bpsw

test_rte:
	RTE
	exit47

success:
	checkpsw2 1 PSW_BITS
	exit0