blob: 2f14ce11979ba946728554d32ead189ca6f8e43f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
|
/* mips target configuration file. */
/* See sim-hload.c. We properly handle LMA. */
#ifdef TARGET_TX3904
#define SIM_HANDLES_LMA 1
/* FIXME: This is unnecessarily necessary: */
#include "ansidecl.h"
#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "sim-module.h"
MODULE_INSTALL_FN dv_sockser_install;
#define MODULE_LIST dv_sockser_install,
#else
#define SIM_HANDLES_LMA 0
#endif
/* Define this if the simulator supports profiling.
See the mips simulator for an example.
This enables the `-p foo' and `-s bar' options.
The target is required to provide sim_set_profile{,_size}. */
#define SIM_HAVE_PROFILE
/* Define this if the simulator uses an instruction cache.
See the h8/300 simulator for an example.
This enables the `-c size' option to set the size of the cache.
The target is required to provide sim_set_simcache_size. */
/* #define SIM_HAVE_SIMCACHE */
/* Define this if the target cpu is bi-endian
and the simulator supports it. */
#define SIM_HAVE_BIENDIAN
/* MIPS uses an unusual format for floating point quiet NaNs. */
#define SIM_QUIET_NAN_NEGATED
|
