aboutsummaryrefslogtreecommitdiff
path: root/sim/mcore/interp.c
blob: 7851acf64590a965186c5649b7c5ec1c1a149f1e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
/* Simulator for Motorola's MCore processor
   Copyright (C) 1999-2019 Free Software Foundation, Inc.
   Contributed by Cygnus Solutions.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"
#include <signal.h>
#include <stdlib.h>
#include <string.h>
#include <sys/times.h>
#include <sys/param.h>
#include <unistd.h>
#include "bfd.h"
#include "gdb/callback.h"
#include "libiberty.h"
#include "gdb/remote-sim.h"

#include "sim-main.h"
#include "sim-base.h"
#include "sim-syscall.h"
#include "sim-options.h"

#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)


static unsigned long
mcore_extract_unsigned_integer (unsigned char *addr, int len)
{
  unsigned long retval;
  unsigned char * p;
  unsigned char * startaddr = (unsigned char *)addr;
  unsigned char * endaddr = startaddr + len;

  if (len > (int) sizeof (unsigned long))
    printf ("That operation is not available on integers of more than %zu bytes.",
	    sizeof (unsigned long));

  /* Start at the most significant end of the integer, and work towards
     the least significant.  */
  retval = 0;

  if (! target_big_endian)
    {
      for (p = endaddr; p > startaddr;)
	retval = (retval << 8) | * -- p;
    }
  else
    {
      for (p = startaddr; p < endaddr;)
	retval = (retval << 8) | * p ++;
    }

  return retval;
}

static void
mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
{
  unsigned char * p;
  unsigned char * startaddr = (unsigned char *)addr;
  unsigned char * endaddr = startaddr + len;

  if (! target_big_endian)
    {
      for (p = startaddr; p < endaddr;)
	{
	  * p ++ = val & 0xff;
	  val >>= 8;
	}
    }
  else
    {
      for (p = endaddr; p > startaddr;)
	{
	  * -- p = val & 0xff;
	  val >>= 8;
	}
    }
}

static int memcycles = 1;

#define gr	cpu->active_gregs
#define cr	cpu->regs.cregs
#define sr	cr[0]
#define vbr	cr[1]
#define esr	cr[2]
#define fsr	cr[3]
#define epc	cr[4]
#define fpc	cr[5]
#define ss0	cr[6]
#define ss1	cr[7]
#define ss2	cr[8]
#define ss3	cr[9]
#define ss4	cr[10]
#define gcr	cr[11]
#define gsr	cr[12]

/* maniuplate the carry bit */
#define C_ON()		(sr & 1)
#define C_VALUE()	(sr & 1)
#define C_OFF()		((sr & 1) == 0)
#define SET_C()		{sr |= 1;}
#define CLR_C()		{sr &= 0xfffffffe;}
#define NEW_C(v)	{CLR_C(); sr |= ((v) & 1);}

#define SR_AF()		((sr >> 1) & 1)
static void set_active_regs (SIM_CPU *cpu)
{
  if (SR_AF())
    cpu->active_gregs = cpu->regs.alt_gregs;
  else
    cpu->active_gregs = cpu->regs.gregs;
}

#define	TRAPCODE	1	/* r1 holds which function we want */
#define	PARM1	2		/* first parameter  */
#define	PARM2	3
#define	PARM3	4
#define	PARM4	5
#define	RET1	2		/* register for return values. */

/* Default to a 8 Mbyte (== 2^23) memory space.  */
#define DEFAULT_MEMORY_SIZE 0x800000

static void
set_initial_gprs (SIM_CPU *cpu)
{
  /* Set up machine just out of reset.  */
  CPU_PC_SET (cpu, 0);
  sr = 0;

  /* Clean out the GPRs and alternate GPRs.  */
  memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs));
  memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs));

  /* Make our register set point to the right place.  */
  set_active_regs (cpu);

  /* ABI specifies initial values for these registers.  */
  gr[0] = DEFAULT_MEMORY_SIZE - 4;

  /* dac fix, the stack address must be 8-byte aligned! */
  gr[0] = gr[0] - gr[0] % 8;
  gr[PARM1] = 0;
  gr[PARM2] = 0;
  gr[PARM3] = 0;
  gr[PARM4] = gr[0];
}

/* Simulate a monitor trap.  */

static void
handle_trap1 (SIM_DESC sd, SIM_CPU *cpu)
{
  /* XXX: We don't pass back the actual errno value.  */
  gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3],
			  gr[PARM4]);
}

static void
process_stub (SIM_DESC sd, SIM_CPU *cpu, int what)
{
  /* These values should match those in libgloss/mcore/syscalls.s.  */
  switch (what)
    {
    case 3:  /* _read */
    case 4:  /* _write */
    case 5:  /* _open */
    case 6:  /* _close */
    case 10: /* _unlink */
    case 19: /* _lseek */
    case 43: /* _times */
      gr[TRAPCODE] = what;
      handle_trap1 (sd, cpu);
      break;

    default:
      if (STATE_VERBOSE_P (sd))
	fprintf (stderr, "Unhandled stub opcode: %d\n", what);
      break;
    }
}

static void
util (SIM_DESC sd, SIM_CPU *cpu, unsigned what)
{
  switch (what)
    {
    case 0:	/* exit */
      sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]);
      break;

    case 1:	/* printf */
      if (STATE_VERBOSE_P (sd))
	fprintf (stderr, "WARNING: printf unimplemented\n");
      break;

    case 2:	/* scanf */
      if (STATE_VERBOSE_P (sd))
	fprintf (stderr, "WARNING: scanf unimplemented\n");
      break;

    case 3:	/* utime */
      gr[RET1] = cpu->insts;
      break;

    case 0xFF:
      process_stub (sd, cpu, gr[1]);
      break;

    default:
      if (STATE_VERBOSE_P (sd))
	fprintf (stderr, "Unhandled util code: %x\n", what);
      break;
    }
}

/* For figuring out whether we carried; addc/subc use this. */
static int
iu_carry (unsigned long a, unsigned long b, int cin)
{
  unsigned long	x;

  x = (a & 0xffff) + (b & 0xffff) + cin;
  x = (x >> 16) + (a >> 16) + (b >> 16);
  x >>= 16;

  return (x != 0);
}

/* TODO: Convert to common watchpoints.  */
#undef WATCHFUNCTIONS
#ifdef WATCHFUNCTIONS

#define MAXWL 80
word WL[MAXWL];
char * WLstr[MAXWL];

int ENDWL=0;
int WLincyc;
int WLcyc[MAXWL];
int WLcnts[MAXWL];
int WLmax[MAXWL];
int WLmin[MAXWL];
word WLendpc;
int WLbcyc;
int WLW;
#endif

#define RD	(inst        & 0xF)
#define RS	((inst >> 4) & 0xF)
#define RX	((inst >> 8) & 0xF)
#define IMM5	((inst >> 4) & 0x1F)
#define IMM4	((inst) & 0xF)

#define rbat(X)	sim_core_read_1 (cpu, 0, read_map, X)
#define rhat(X)	sim_core_read_2 (cpu, 0, read_map, X)
#define rlat(X)	sim_core_read_4 (cpu, 0, read_map, X)
#define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
#define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
#define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)

static int tracing = 0;

#define ILLEGAL() \
  sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL)

static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
  int needfetch;
  word ibuf;
  word pc;
  unsigned short inst;
  int memops;
  int bonus_cycles;
  int insts;
  int w;
  int cycs;
#ifdef WATCHFUNCTIONS
  word WLhash;
#endif

  pc = CPU_PC_GET (cpu);

  /* Fetch the initial instructions that we'll decode. */
  ibuf = rlat (pc & 0xFFFFFFFC);
  needfetch = 0;

  memops = 0;
  bonus_cycles = 0;
  insts = 0;

  /* make our register set point to the right place */
  set_active_regs (cpu);

#ifdef WATCHFUNCTIONS
  /* make a hash to speed exec loop, hope it's nonzero */
  WLhash = 0xFFFFFFFF;

  for (w = 1; w <= ENDWL; w++)
    WLhash = WLhash & WL[w];
#endif

  /* TODO: Unindent this block.  */
    {
      word oldpc;

      insts ++;

      if (pc & 02)
	{
	  if (! target_big_endian)
	    inst = ibuf >> 16;
	  else
	    inst = ibuf & 0xFFFF;
	  needfetch = 1;
	}
      else
	{
	  if (! target_big_endian)
	    inst = ibuf & 0xFFFF;
	  else
	    inst = ibuf >> 16;
	}

#ifdef WATCHFUNCTIONS
      /* now scan list of watch addresses, if match, count it and
	 note return address and count cycles until pc=return address */

      if ((WLincyc == 1) && (pc == WLendpc))
	{
	  cycs = (cpu->cycles + (insts + bonus_cycles +
				       (memops * memcycles)) - WLbcyc);

	  if (WLcnts[WLW] == 1)
	    {
	      WLmax[WLW] = cycs;
	      WLmin[WLW] = cycs;
	      WLcyc[WLW] = 0;
	    }

	  if (cycs > WLmax[WLW])
	    {
	      WLmax[WLW] = cycs;
	    }

	  if (cycs < WLmin[WLW])
	    {
	      WLmin[WLW] = cycs;
	    }

	  WLcyc[WLW] += cycs;
	  WLincyc = 0;
	  WLendpc = 0;
	}

      /* Optimize with a hash to speed loop.  */
      if (WLincyc == 0)
	{
          if ((WLhash == 0) || ((WLhash & pc) != 0))
	    {
	      for (w=1; w <= ENDWL; w++)
		{
		  if (pc == WL[w])
		    {
		      WLcnts[w]++;
		      WLbcyc = cpu->cycles + insts
			+ bonus_cycles + (memops * memcycles);
		      WLendpc = gr[15];
		      WLincyc = 1;
		      WLW = w;
		      break;
		    }
		}
	    }
	}
#endif

      if (tracing)
	fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst);

      oldpc = pc;

      pc += 2;

      switch (inst >> 8)
	{
	case 0x00:
	  switch RS
	    {
	    case 0x0:
	      switch RD
		{
		case 0x0:				/* bkpt */
		  pc -= 2;
		  sim_engine_halt (sd, cpu, NULL, pc - 2,
				   sim_stopped, SIM_SIGTRAP);
		  break;

		case 0x1:				/* sync */
		  break;

		case 0x2:				/* rte */
		  pc = epc;
		  sr = esr;
		  needfetch = 1;

		  set_active_regs (cpu);
		  break;

		case 0x3:				/* rfi */
		  pc = fpc;
		  sr = fsr;
		  needfetch = 1;

		  set_active_regs (cpu);
		  break;

		case 0x4:				/* stop */
		  if (STATE_VERBOSE_P (sd))
		    fprintf (stderr, "WARNING: stop unimplemented\n");
		  break;

		case 0x5:				/* wait */
		  if (STATE_VERBOSE_P (sd))
		    fprintf (stderr, "WARNING: wait unimplemented\n");
		  break;

		case 0x6:				/* doze */
		  if (STATE_VERBOSE_P (sd))
		    fprintf (stderr, "WARNING: doze unimplemented\n");
		  break;

		case 0x7:
		  ILLEGAL ();				/* illegal */
		  break;

		case 0x8:				/* trap 0 */
		case 0xA:				/* trap 2 */
		case 0xB:				/* trap 3 */
		  sim_engine_halt (sd, cpu, NULL, pc,
				   sim_stopped, SIM_SIGTRAP);
		  break;

		case 0xC:				/* trap 4 */
		case 0xD:				/* trap 5 */
		case 0xE:				/* trap 6 */
		  ILLEGAL ();				/* illegal */
		  break;

		case 0xF: 				/* trap 7 */
		  sim_engine_halt (sd, cpu, NULL, pc,	/* integer div-by-0 */
				   sim_stopped, SIM_SIGTRAP);
		  break;

		case 0x9:				/* trap 1 */
		  handle_trap1 (sd, cpu);
		  break;
		}
	      break;

	    case 0x1:
	      ILLEGAL ();				/* illegal */
	      break;

	    case 0x2:					/* mvc */
	      gr[RD] = C_VALUE();
	      break;
	    case 0x3:					/* mvcv */
	      gr[RD] = C_OFF();
	      break;
	    case 0x4:					/* ldq */
	      {
		word addr = gr[RD];
		int regno = 4;			/* always r4-r7 */

		bonus_cycles++;
		memops += 4;
		do
		  {
		    gr[regno] = rlat (addr);
		    addr += 4;
		    regno++;
		  }
		while ((regno&0x3) != 0);
	      }
	      break;
	    case 0x5:					/* stq */
	      {
		word addr = gr[RD];
		int regno = 4;			/* always r4-r7 */

		memops += 4;
		bonus_cycles++;
		do
		  {
		    wlat (addr, gr[regno]);
		    addr += 4;
		    regno++;
		  }
		while ((regno & 0x3) != 0);
	      }
	      break;
	    case 0x6:					/* ldm */
	      {
		word addr = gr[0];
		int regno = RD;

		/* bonus cycle is really only needed if
		   the next insn shifts the last reg loaded.

		   bonus_cycles++;
		*/
		memops += 16-regno;
		while (regno <= 0xF)
		  {
		    gr[regno] = rlat (addr);
		    addr += 4;
		    regno++;
		  }
	      }
	      break;
	    case 0x7:					/* stm */
	      {
		word addr = gr[0];
		int regno = RD;

		/* this should be removed! */
		/*  bonus_cycles ++; */

		memops += 16 - regno;
		while (regno <= 0xF)
		  {
		    wlat (addr, gr[regno]);
		    addr += 4;
		    regno++;
		  }
	      }
	      break;

	    case 0x8:					/* dect */
	      gr[RD] -= C_VALUE();
	      break;
	    case 0x9:					/* decf */
	      gr[RD] -= C_OFF();
	      break;
	    case 0xA:					/* inct */
	      gr[RD] += C_VALUE();
	      break;
	    case 0xB:					/* incf */
	      gr[RD] += C_OFF();
	      break;
	    case 0xC:					/* jmp */
	      pc = gr[RD];
	      if (tracing && RD == 15)
		fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n",
			 gr[2], gr[3]);
	      bonus_cycles++;
	      needfetch = 1;
	      break;
	    case 0xD:					/* jsr */
	      gr[15] = pc;
	      pc = gr[RD];
	      bonus_cycles++;
	      needfetch = 1;
	      break;
	    case 0xE:					/* ff1 */
	      {
		word tmp, i;
		tmp = gr[RD];
		for (i = 0; !(tmp & 0x80000000) && i < 32; i++)
		  tmp <<= 1;
		gr[RD] = i;
	      }
	      break;
	    case 0xF:					/* brev */
	      {
		word tmp;
		tmp = gr[RD];
		tmp = ((tmp & 0xaaaaaaaa) >>  1) | ((tmp & 0x55555555) <<  1);
		tmp = ((tmp & 0xcccccccc) >>  2) | ((tmp & 0x33333333) <<  2);
		tmp = ((tmp & 0xf0f0f0f0) >>  4) | ((tmp & 0x0f0f0f0f) <<  4);
		tmp = ((tmp & 0xff00ff00) >>  8) | ((tmp & 0x00ff00ff) <<  8);
		gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16);
	      }
	      break;
	    }
	  break;
	case 0x01:
	  switch RS
	    {
	    case 0x0:					/* xtrb3 */
	      gr[1] = (gr[RD]) & 0xFF;
	      NEW_C (gr[RD] != 0);
	      break;
	    case 0x1:					/* xtrb2 */
	      gr[1] = (gr[RD]>>8) & 0xFF;
	      NEW_C (gr[RD] != 0);
	      break;
	    case 0x2:					/* xtrb1 */
	      gr[1] = (gr[RD]>>16) & 0xFF;
	      NEW_C (gr[RD] != 0);
	      break;
	    case 0x3:					/* xtrb0 */
	      gr[1] = (gr[RD]>>24) & 0xFF;
	      NEW_C (gr[RD] != 0);
	      break;
	    case 0x4:					/* zextb */
	      gr[RD] &= 0x000000FF;
	      break;
	    case 0x5:					/* sextb */
	      {
		long tmp;
		tmp = gr[RD];
		tmp <<= 24;
		tmp >>= 24;
		gr[RD] = tmp;
	      }
	      break;
	    case 0x6:					/* zexth */
	      gr[RD] &= 0x0000FFFF;
	      break;
	    case 0x7:					/* sexth */
	      {
		long tmp;
		tmp = gr[RD];
		tmp <<= 16;
		tmp >>= 16;
		gr[RD] = tmp;
	      }
	      break;
	    case 0x8:					/* declt */
	      --gr[RD];
	      NEW_C ((long)gr[RD] < 0);
	      break;
	    case 0x9:					/* tstnbz */
	      {
		word tmp = gr[RD];
		NEW_C ((tmp & 0xFF000000) != 0 &&
		       (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 &&
		       (tmp & 0x000000FF) != 0);
	      }
	      break;
	    case 0xA:					/* decgt */
	      --gr[RD];
	      NEW_C ((long)gr[RD] > 0);
	      break;
	    case 0xB:					/* decne */
	      --gr[RD];
	      NEW_C ((long)gr[RD] != 0);
	      break;
	    case 0xC:					/* clrt */
	      if (C_ON())
		gr[RD] = 0;
	      break;
	    case 0xD:					/* clrf */
	      if (C_OFF())
		gr[RD] = 0;
	      break;
	    case 0xE:					/* abs */
	      if (gr[RD] & 0x80000000)
		gr[RD] = ~gr[RD] + 1;
	      break;
	    case 0xF:					/* not */
	      gr[RD] = ~gr[RD];
	      break;
	    }
	  break;
	case 0x02:					/* movt */
	  if (C_ON())
	    gr[RD] = gr[RS];
	  break;
	case 0x03:					/* mult */
	  /* consume 2 bits per cycle from rs, until rs is 0 */
	  {
	    unsigned int t = gr[RS];
	    int ticks;
	    for (ticks = 0; t != 0 ; t >>= 2)
	      ticks++;
	    bonus_cycles += ticks;
	  }
	  bonus_cycles += 2;  /* min. is 3, so add 2, plus ticks above */
	  if (tracing)
	    fprintf (stderr, "  mult %lx by %lx to give %lx",
		     gr[RD], gr[RS], gr[RD] * gr[RS]);
	  gr[RD] = gr[RD] * gr[RS];
	  break;
	case 0x04:					/* loopt */
	  if (C_ON())
	    {
	      pc += (IMM4 << 1) - 32;
	      bonus_cycles ++;
	      needfetch = 1;
	    }
	  --gr[RS];				/* not RD! */
	  NEW_C (((long)gr[RS]) > 0);
	  break;
	case 0x05:					/* subu */
	  gr[RD] -= gr[RS];
	  break;
	case 0x06:					/* addc */
	  {
	    unsigned long tmp, a, b;
	    a = gr[RD];
	    b = gr[RS];
	    gr[RD] = a + b + C_VALUE ();
	    tmp = iu_carry (a, b, C_VALUE ());
	    NEW_C (tmp);
	  }
	  break;
	case 0x07:					/* subc */
	  {
	    unsigned long tmp, a, b;
	    a = gr[RD];
	    b = gr[RS];
	    gr[RD] = a - b + C_VALUE () - 1;
	    tmp = iu_carry (a,~b, C_VALUE ());
	    NEW_C (tmp);
	  }
	  break;
	case 0x08:					/* illegal */
	case 0x09:					/* illegal*/
	  ILLEGAL ();
	  break;
	case 0x0A:					/* movf */
	  if (C_OFF())
	    gr[RD] = gr[RS];
	  break;
	case 0x0B:					/* lsr */
	  {
	    unsigned long dst, src;
	    dst = gr[RD];
	    src = gr[RS];
	    /* We must not rely solely upon the native shift operations, since they
	       may not match the M*Core's behaviour on boundary conditions.  */
	    dst = src > 31 ? 0 : dst >> src;
	    gr[RD] = dst;
	  }
	  break;
	case 0x0C:					/* cmphs */
	  NEW_C ((unsigned long )gr[RD] >=
		 (unsigned long)gr[RS]);
	  break;
	case 0x0D:					/* cmplt */
	  NEW_C ((long)gr[RD] < (long)gr[RS]);
	  break;
	case 0x0E:					/* tst */
	  NEW_C ((gr[RD] & gr[RS]) != 0);
	  break;
	case 0x0F:					/* cmpne */
	  NEW_C (gr[RD] != gr[RS]);
	  break;
	case 0x10: case 0x11:				/* mfcr */
	  {
	    unsigned r;
	    r = IMM5;
	    if (r <= LAST_VALID_CREG)
	      gr[RD] = cr[r];
	    else
	      ILLEGAL ();
	  }
	  break;

	case 0x12:					/* mov */
	  gr[RD] = gr[RS];
	  if (tracing)
	    fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD);
	  break;

	case 0x13:					/* bgenr */
	  if (gr[RS] & 0x20)
	    gr[RD] = 0;
	  else
	    gr[RD] = 1 << (gr[RS] & 0x1F);
	  break;

	case 0x14:					/* rsub */
	  gr[RD] = gr[RS] - gr[RD];
	  break;

	case 0x15:					/* ixw */
	  gr[RD] += gr[RS]<<2;
	  break;

	case 0x16:					/* and */
	  gr[RD] &= gr[RS];
	  break;

	case 0x17:					/* xor */
	  gr[RD] ^= gr[RS];
	  break;

	case 0x18: case 0x19:				/* mtcr */
	  {
	    unsigned r;
	    r = IMM5;
	    if (r <= LAST_VALID_CREG)
	      cr[r] = gr[RD];
	    else
	      ILLEGAL ();

	    /* we might have changed register sets... */
	    set_active_regs (cpu);
	  }
	  break;

	case 0x1A:					/* asr */
	  /* We must not rely solely upon the native shift operations, since they
	     may not match the M*Core's behaviour on boundary conditions.  */
	  if (gr[RS] > 30)
	    gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0;
	  else
	    gr[RD] = (long) gr[RD] >> gr[RS];
	  break;

	case 0x1B:					/* lsl */
	  /* We must not rely solely upon the native shift operations, since they
	     may not match the M*Core's behaviour on boundary conditions.  */
	  gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS];
	  break;

	case 0x1C:					/* addu */
	  gr[RD] += gr[RS];
	  break;

	case 0x1D:					/* ixh */
	  gr[RD] += gr[RS] << 1;
	  break;

	case 0x1E:					/* or */
	  gr[RD] |= gr[RS];
	  break;

	case 0x1F:					/* andn */
	  gr[RD] &= ~gr[RS];
	  break;
	case 0x20: case 0x21:				/* addi */
	  gr[RD] =
	    gr[RD] + (IMM5 + 1);
	  break;
	case 0x22: case 0x23:				/* cmplti */
	  {
	    int tmp = (IMM5 + 1);
	    if (gr[RD] < tmp)
	      {
	        SET_C();
	      }
	    else
	      {
	        CLR_C();
	      }
	  }
	  break;
	case 0x24: case 0x25:				/* subi */
	  gr[RD] =
	    gr[RD] - (IMM5 + 1);
	  break;
	case 0x26: case 0x27:				/* illegal */
	  ILLEGAL ();
	  break;
	case 0x28: case 0x29:				/* rsubi */
	  gr[RD] =
	    IMM5 - gr[RD];
	  break;
	case 0x2A: case 0x2B:				/* cmpnei */
	  if (gr[RD] != IMM5)
	    {
	      SET_C();
	    }
	  else
	    {
	      CLR_C();
	    }
	  break;

	case 0x2C: case 0x2D:				/* bmaski, divu */
	  {
	    unsigned imm = IMM5;

	    if (imm == 1)
	      {
		int exe;
		int rxnlz, r1nlz;
		unsigned int rx, r1;

		rx = gr[RD];
		r1 = gr[1];
		exe = 0;

		/* unsigned divide */
		gr[RD] = (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] );

		/* compute bonus_cycles for divu */
		for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++)
		  r1 = r1 << 1;

		for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++)
		  rx = rx << 1;

		if (r1nlz < rxnlz)
		  exe += 4;
		else
		  exe += 5 + r1nlz - rxnlz;

		if (exe >= (2 * memcycles - 1))
		  {
		    bonus_cycles += exe - (2 * memcycles) + 1;
		  }
	      }
	    else if (imm == 0 || imm >= 8)
	      {
		/* bmaski */
		if (imm == 0)
		  gr[RD] = -1;
		else
		  gr[RD] = (1 << imm) - 1;
	      }
	    else
	      {
		/* illegal */
		ILLEGAL ();
	      }
	  }
	  break;
	case 0x2E: case 0x2F:				/* andi */
	  gr[RD] = gr[RD] & IMM5;
	  break;
	case 0x30: case 0x31:				/* bclri */
	  gr[RD] = gr[RD] & ~(1<<IMM5);
	  break;
	case 0x32: case 0x33:				/* bgeni, divs */
	  {
	    unsigned imm = IMM5;
	    if (imm == 1)
	      {
		int exe,sc;
		int rxnlz, r1nlz;
		signed int rx, r1;

		/* compute bonus_cycles for divu */
		rx = gr[RD];
		r1 = gr[1];
		exe = 0;

		if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0)))
		  sc = 1;
		else
		  sc = 0;

		rx = abs (rx);
		r1 = abs (r1);

		/* signed divide, general registers are of type int, so / op is OK */
		gr[RD] = gr[RD] / gr[1];

		for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ )
		  r1 = r1 << 1;

		for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ )
		  rx = rx << 1;

		if (r1nlz < rxnlz)
		  exe += 5;
		else
		  exe += 6 + r1nlz - rxnlz + sc;

		if (exe >= (2 * memcycles - 1))
		  {
		    bonus_cycles += exe - (2 * memcycles) + 1;
		  }
	      }
	    else if (imm >= 7)
	      {
		/* bgeni */
		gr[RD] = (1 << IMM5);
	      }
	    else
	      {
		/* illegal */
		ILLEGAL ();
	      }
	    break;
	  }
	case 0x34: case 0x35:				/* bseti */
	  gr[RD] = gr[RD] | (1 << IMM5);
	  break;
	case 0x36: case 0x37:				/* btsti */
	  NEW_C (gr[RD] >> IMM5);
	  break;
	case 0x38: case 0x39:				/* xsr, rotli */
	  {
	    unsigned imm = IMM5;
	    unsigned long tmp = gr[RD];
	    if (imm == 0)
	      {
		word cbit;
		cbit = C_VALUE();
		NEW_C (tmp);
		gr[RD] = (cbit << 31) | (tmp >> 1);
	      }
	    else
	      gr[RD] = (tmp << imm) | (tmp >> (32 - imm));
	  }
	  break;
	case 0x3A: case 0x3B:				/* asrc, asri */
	  {
	    unsigned imm = IMM5;
	    long tmp = gr[RD];
	    if (imm == 0)
	      {
		NEW_C (tmp);
		gr[RD] = tmp >> 1;
	      }
	    else
	      gr[RD] = tmp >> imm;
	  }
	  break;
	case 0x3C: case 0x3D:				/* lslc, lsli */
	  {
	    unsigned imm = IMM5;
	    unsigned long tmp = gr[RD];
	    if (imm == 0)
	      {
		NEW_C (tmp >> 31);
		gr[RD] = tmp << 1;
	      }
	    else
	      gr[RD] = tmp << imm;
	  }
	  break;
	case 0x3E: case 0x3F:				/* lsrc, lsri */
	  {
	    unsigned imm = IMM5;
	    unsigned long tmp = gr[RD];
	    if (imm == 0)
	      {
		NEW_C (tmp);
		gr[RD] = tmp >> 1;
	      }
	    else
	      gr[RD] = tmp >> imm;
	  }
	  break;
	case 0x40: case 0x41: case 0x42: case 0x43:
	case 0x44: case 0x45: case 0x46: case 0x47:
	case 0x48: case 0x49: case 0x4A: case 0x4B:
	case 0x4C: case 0x4D: case 0x4E: case 0x4F:
	  ILLEGAL ();
	  break;
	case 0x50:
	  util (sd, cpu, inst & 0xFF);
	  break;
	case 0x51: case 0x52: case 0x53:
	case 0x54: case 0x55: case 0x56: case 0x57:
	case 0x58: case 0x59: case 0x5A: case 0x5B:
	case 0x5C: case 0x5D: case 0x5E: case 0x5F:
	  ILLEGAL ();
	  break;
	case 0x60: case 0x61: case 0x62: case 0x63:	/* movi  */
	case 0x64: case 0x65: case 0x66: case 0x67:
	  gr[RD] = (inst >> 4) & 0x7F;
	  break;
	case 0x68: case 0x69: case 0x6A: case 0x6B:
	case 0x6C: case 0x6D: case 0x6E: case 0x6F:	/* illegal */
	  ILLEGAL ();
	  break;
	case 0x71: case 0x72: case 0x73:
	case 0x74: case 0x75: case 0x76: case 0x77:
	case 0x78: case 0x79: case 0x7A: case 0x7B:
	case 0x7C: case 0x7D: case 0x7E:		/* lrw */
	  gr[RX] =  rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	  if (tracing)
	    fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d",
		     rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC),
		     (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX);
	  memops++;
	  break;
	case 0x7F:					/* jsri */
	  gr[15] = pc;
	  if (tracing)
	    fprintf (stderr,
		     "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n",
		     gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]);
	case 0x70:					/* jmpi */
	  pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
	  memops++;
	  bonus_cycles++;
	  needfetch = 1;
	  break;

	case 0x80: case 0x81: case 0x82: case 0x83:
	case 0x84: case 0x85: case 0x86: case 0x87:
	case 0x88: case 0x89: case 0x8A: case 0x8B:
	case 0x8C: case 0x8D: case 0x8E: case 0x8F:	/* ld */
	  gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C));
	  if (tracing)
	    fprintf (stderr, "load reg %d from 0x%lx with 0x%lx",
		     RX,
		     gr[RD] + ((inst >> 2) & 0x003C), gr[RX]);
	  memops++;
	  break;
	case 0x90: case 0x91: case 0x92: case 0x93:
	case 0x94: case 0x95: case 0x96: case 0x97:
	case 0x98: case 0x99: case 0x9A: case 0x9B:
	case 0x9C: case 0x9D: case 0x9E: case 0x9F:	/* st */
	  wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]);
	  if (tracing)
	    fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx",
		     RX, gr[RX],
		     gr[RD] + ((inst >> 2) & 0x003C));
	  memops++;
	  break;
	case 0xA0: case 0xA1: case 0xA2: case 0xA3:
	case 0xA4: case 0xA5: case 0xA6: case 0xA7:
	case 0xA8: case 0xA9: case 0xAA: case 0xAB:
	case 0xAC: case 0xAD: case 0xAE: case 0xAF:	/* ld.b */
	  gr[RX] = rbat (gr[RD] + RS);
	  memops++;
	  break;
	case 0xB0: case 0xB1: case 0xB2: case 0xB3:
	case 0xB4: case 0xB5: case 0xB6: case 0xB7:
	case 0xB8: case 0xB9: case 0xBA: case 0xBB:
	case 0xBC: case 0xBD: case 0xBE: case 0xBF:	/* st.b */
	  wbat (gr[RD] + RS, gr[RX]);
	  memops++;
	  break;
	case 0xC0: case 0xC1: case 0xC2: case 0xC3:
	case 0xC4: case 0xC5: case 0xC6: case 0xC7:
	case 0xC8: case 0xC9: case 0xCA: case 0xCB:
	case 0xCC: case 0xCD: case 0xCE: case 0xCF:	/* ld.h */
	  gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E));
	  memops++;
	  break;
	case 0xD0: case 0xD1: case 0xD2: case 0xD3:
	case 0xD4: case 0xD5: case 0xD6: case 0xD7:
	case 0xD8: case 0xD9: case 0xDA: case 0xDB:
	case 0xDC: case 0xDD: case 0xDE: case 0xDF:	/* st.h */
	  what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]);
	  memops++;
	  break;
	case 0xE8: case 0xE9: case 0xEA: case 0xEB:
	case 0xEC: case 0xED: case 0xEE: case 0xEF:	/* bf */
	  if (C_OFF())
	    {
	      int disp;
	      disp = inst & 0x03FF;
	      if (inst & 0x0400)
		disp |= 0xFFFFFC00;
	      pc += disp<<1;
	      bonus_cycles++;
	      needfetch = 1;
	    }
	  break;
	case 0xE0: case 0xE1: case 0xE2: case 0xE3:
	case 0xE4: case 0xE5: case 0xE6: case 0xE7:	/* bt */
	  if (C_ON())
	    {
	      int disp;
	      disp = inst & 0x03FF;
	      if (inst & 0x0400)
		disp |= 0xFFFFFC00;
	      pc += disp<<1;
	      bonus_cycles++;
	      needfetch = 1;
	    }
	  break;

	case 0xF8: case 0xF9: case 0xFA: case 0xFB:
	case 0xFC: case 0xFD: case 0xFE: case 0xFF:	/* bsr */
	  gr[15] = pc;
	case 0xF0: case 0xF1: case 0xF2: case 0xF3:
	case 0xF4: case 0xF5: case 0xF6: case 0xF7:	/* br */
	  {
	    int disp;
	    disp = inst & 0x03FF;
	    if (inst & 0x0400)
	      disp |= 0xFFFFFC00;
	    pc += disp<<1;
	    bonus_cycles++;
	    needfetch = 1;
	  }
	  break;

	}

      if (tracing)
	fprintf (stderr, "\n");

      if (needfetch)
	{
	  ibuf = rlat (pc & 0xFFFFFFFC);
	  needfetch = 0;
	}
    }

  /* Hide away the things we've cached while executing.  */
  CPU_PC_SET (cpu, pc);
  cpu->insts += insts;		/* instructions done ... */
  cpu->cycles += insts;		/* and each takes a cycle */
  cpu->cycles += bonus_cycles;	/* and extra cycles for branches */
  cpu->cycles += memops * memcycles;	/* and memop cycle delays */
}

void
sim_engine_run (SIM_DESC sd,
		int next_cpu_nr,  /* ignore  */
		int nr_cpus,      /* ignore  */
		int siggnal)      /* ignore  */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  cpu = STATE_CPU (sd, 0);

  while (1)
    {
      step_once (sd, cpu);
      if (sim_events_tick (sd))
	sim_events_process (sd);
    }
}

static int
mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  if (rn < NUM_MCORE_REGS && rn >= 0)
    {
      if (length == 4)
	{
	  long ival;

	  /* misalignment safe */
	  ival = mcore_extract_unsigned_integer (memory, 4);
	  cpu->asints[rn] = ival;
	}

      return 4;
    }
  else
    return 0;
}

static int
mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  if (rn < NUM_MCORE_REGS && rn >= 0)
    {
      if (length == 4)
	{
	  long ival = cpu->asints[rn];

	  /* misalignment-safe */
	  mcore_store_unsigned_integer (memory, 4, ival);
	}

      return 4;
    }
  else
    return 0;
}

void
sim_info (SIM_DESC sd, int verbose)
{
  SIM_CPU *cpu = STATE_CPU (sd, 0);
#ifdef WATCHFUNCTIONS
  int w, wcyc;
#endif
  double virttime = cpu->cycles / 36.0e6;
  host_callback *callback = STATE_CALLBACK (sd);

  callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n",
			     cpu->insts);
  callback->printf_filtered (callback, "# cycles                 %10d\n",
			     cpu->cycles);
  callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
			     cpu->stalls);
  callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
			     virttime);

#ifdef WATCHFUNCTIONS
  callback->printf_filtered (callback, "\nNumber of watched functions: %d\n",
			     ENDWL);

  wcyc = 0;

  for (w = 1; w <= ENDWL; w++)
    {
      callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]);
      callback->printf_filtered (callback, "  calls = %d, cycles = %d\n",
				 WLcnts[w],WLcyc[w]);

      if (WLcnts[w] != 0)
	callback->printf_filtered (callback,
				   "  maxcpc = %d, mincpc = %d, avecpc = %d\n",
				   WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]);
      wcyc += WLcyc[w];
    }

  callback->printf_filtered (callback,
			     "Total cycles for watched functions: %d\n",wcyc);
#endif
}

static sim_cia
mcore_pc_get (sim_cpu *cpu)
{
  return cpu->regs.pc;
}

static void
mcore_pc_set (sim_cpu *cpu, sim_cia pc)
{
  cpu->regs.pc = pc;
}

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);
  sim_cpu_free_all (sd);
  sim_state_free (sd);
}

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *cb,
	  struct bfd *abfd, char * const *argv)
{
  int i;
  SIM_DESC sd = sim_state_alloc (kind, cb);
  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Configure/verify the target byte order and other runtime
     configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      sim_module_uninstall (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
	 file descriptor leaks, etc.  */
      sim_module_uninstall (sd);
      return 0;
    }

  /* CPU specific initialization.  */
  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
    {
      SIM_CPU *cpu = STATE_CPU (sd, i);

      CPU_REG_FETCH (cpu) = mcore_reg_fetch;
      CPU_REG_STORE (cpu) = mcore_reg_store;
      CPU_PC_FETCH (cpu) = mcore_pc_get;
      CPU_PC_STORE (cpu) = mcore_pc_set;

      set_initial_gprs (cpu);	/* Reset the GPR registers.  */
    }

  /* Default to a 8 Mbyte (== 2^23) memory space.  */
  sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE);

  return sd;
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
		     char * const *argv, char * const *env)
{
  SIM_CPU *cpu = STATE_CPU (sd, 0);
  char ** avp;
  int nargs = 0;
  int nenv = 0;
  int s_length;
  int l;
  unsigned long strings;
  unsigned long pointers;
  unsigned long hi_stack;


  /* Set the initial register set.  */
  set_initial_gprs (cpu);

  hi_stack = DEFAULT_MEMORY_SIZE - 4;
  CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd));

  /* Calculate the argument and environment strings.  */
  s_length = 0;
  nargs = 0;
  avp = argv;
  while (avp && *avp)
    {
      l = strlen (*avp) + 1;	/* include the null */
      s_length += (l + 3) & ~3;	/* make it a 4 byte boundary */
      nargs++; avp++;
    }

  nenv = 0;
  avp = env;
  while (avp && *avp)
    {
      l = strlen (*avp) + 1;	/* include the null */
      s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */
      nenv++; avp++;
    }

  /* Claim some memory for the pointers and strings. */
  pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1);
  pointers &= ~3;		/* must be 4-byte aligned */
  gr[0] = pointers;

  strings = gr[0] - s_length;
  strings &= ~3;		/* want to make it 4-byte aligned */
  gr[0] = strings;
  /* dac fix, the stack address must be 8-byte aligned! */
  gr[0] = gr[0] - gr[0] % 8;

  /* Loop through the arguments and fill them in.  */
  gr[PARM1] = nargs;
  if (nargs == 0)
    {
      /* No strings to fill in.  */
      gr[PARM2] = 0;
    }
  else
    {
      gr[PARM2] = pointers;
      avp = argv;
      while (avp && *avp)
	{
	  /* Save where we're putting it.  */
	  wlat (pointers, strings);

	  /* Copy the string.  */
	  l = strlen (* avp) + 1;
	  sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l);

	  /* Bump the pointers.  */
	  avp++;
	  pointers += 4;
	  strings += l+1;
	}

      /* A null to finish the list.  */
      wlat (pointers, 0);
      pointers += 4;
    }

  /* Now do the environment pointers.  */
  if (nenv == 0)
    {
      /* No strings to fill in.  */
      gr[PARM3] = 0;
    }
  else
    {
      gr[PARM3] = pointers;
      avp = env;

      while (avp && *avp)
	{
	  /* Save where we're putting it.  */
	  wlat (pointers, strings);

	  /* Copy the string.  */
	  l = strlen (* avp) + 1;
	  sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l);

	  /* Bump the pointers.  */
	  avp++;
	  pointers += 4;
	  strings += l+1;
	}

      /* A null to finish the list.  */
      wlat (pointers, 0);
      pointers += 4;
    }

  return SIM_RC_OK;
}