1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
|
/* collection of junk waiting time to sort out
Copyright (C) 1996-2019 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef M32R_SIM_H
#define M32R_SIM_H
/* GDB register numbers. */
#define PSW_REGNUM 16
#define CBR_REGNUM 17
#define SPI_REGNUM 18
#define SPU_REGNUM 19
#define BPC_REGNUM 20
#define PC_REGNUM 21
#define ACCL_REGNUM 22
#define ACCH_REGNUM 23
#define ACC1L_REGNUM 24
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
#define EVB_REGNUM 28
extern int m32r_decode_gdb_ctrl_regnum (int);
/* Cover macros for hardware accesses.
FIXME: Eventually move to cgen. */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
#ifndef GET_H_CR
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
#define GET_H_CR(regno) \
XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
#endif
#ifndef GET_H_PSW
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
#define GET_H_PSW() \
XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
#endif
#ifndef GET_H_ACCUM
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
#define GET_H_ACCUM() \
XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
#endif
/* Misc. profile data. */
typedef struct {
/* nop insn slot filler count */
unsigned int fillnop_count;
/* number of parallel insns */
unsigned int parallel_count;
/* FIXME: generalize this to handle all insn lengths, move to common. */
/* number of short insns, not including parallel ones */
unsigned int short_count;
/* number of long insns */
unsigned int long_count;
/* Working area for computing cycle counts. */
unsigned long insn_cycles; /* FIXME: delete */
unsigned long cti_stall;
unsigned long load_stall;
unsigned long biggest_cycles;
/* Bitmask of registers loaded by previous insn. */
unsigned int load_regs;
/* Bitmask of registers loaded by current insn. */
unsigned int load_regs_pending;
} M32R_MISC_PROFILE;
/* Initialize the working area. */
void m32r_init_insn_cycles (SIM_CPU *, int);
/* Update the totals for the insn. */
void m32r_record_insn_cycles (SIM_CPU *, int);
/* This is invoked by the nop pattern in the .cpu file. */
#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
do { \
if (PROFILE_INSN_P (cpu) \
&& (addr & 3) != 0) \
++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_PARINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_SHORTINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_LONGINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
} while (0)
#define GETTWI GETTSI
#define SETTWI SETTSI
/* Additional execution support. */
/* Hardware/device support.
??? Will eventually want to move device stuff to config files. */
/* Exception, Interrupt, and Trap addresses */
#define EIT_SYSBREAK_ADDR 0x10
#define EIT_RSVD_INSN_ADDR 0x20
#define EIT_ADDR_EXCP_ADDR 0x30
#define EIT_TRAP_BASE_ADDR 0x40
#define EIT_EXTERN_ADDR 0x80
#define EIT_RESET_ADDR 0x7ffffff0
#define EIT_WAKEUP_ADDR 0x7ffffff0
/* Special purpose traps. */
#define TRAP_SYSCALL 0
#define TRAP_BREAKPOINT 1
/* Handle the trap insn. */
USI m32r_trap (SIM_CPU *, PCADDR, int);
#endif /* M32R_SIM_H */
|
