aboutsummaryrefslogtreecommitdiff
path: root/sim/m32r/cpu2.h
blob: 6fbed5d0c573333700b1ae4b1c12993dc8821727 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
/* CPU family header for m32r2f.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996-2017 Free Software Foundation, Inc.

This file is part of the GNU simulators.

   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License along
   with this program; if not, see <http://www.gnu.org/licenses/>.

*/

#ifndef CPU_M32R2F_H
#define CPU_M32R2F_H

/* Maximum number of instructions that are fetched at a time.
   This is for LIW type instructions sets (e.g. m32r).  */
#define MAX_LIW_INSNS 2

/* Maximum number of instructions that can be executed in parallel.  */
#define MAX_PARALLEL_INSNS 2

/* The size of an "int" needed to hold an instruction word.
   This is usually 32 bits, but some architectures needs 64 bits.  */
typedef CGEN_INSN_INT CGEN_INSN_WORD;

#include "cgen-engine.h"

/* CPU state information.  */
typedef struct {
  /* Hardware elements.  */
  struct {
  /* program counter */
  USI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) (CPU (h_pc) = (x))
  /* general registers */
  SI h_gr[16];
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  /* control registers */
  USI h_cr[16];
#define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)
#define SET_H_CR(index, x) \
do { \
m32r2f_h_cr_set_handler (current_cpu, (index), (x));\
;} while (0)
  /* accumulator */
  DI h_accum;
#define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)
#define SET_H_ACCUM(x) \
do { \
m32r2f_h_accum_set_handler (current_cpu, (x));\
;} while (0)
  /* accumulators */
  DI h_accums[2];
#define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index)
#define SET_H_ACCUMS(index, x) \
do { \
m32r2f_h_accums_set_handler (current_cpu, (index), (x));\
;} while (0)
  /* condition bit */
  BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
  /* psw part of psw */
  UQI h_psw;
#define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)
#define SET_H_PSW(x) \
do { \
m32r2f_h_psw_set_handler (current_cpu, (x));\
;} while (0)
  /* backup psw */
  UQI h_bpsw;
#define GET_H_BPSW() CPU (h_bpsw)
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  /* backup bpsw */
  UQI h_bbpsw;
#define GET_H_BBPSW() CPU (h_bbpsw)
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  /* lock */
  BI h_lock;
#define GET_H_LOCK() CPU (h_lock)
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
  } hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} M32R2F_CPU_DATA;

/* Cover fns for register access.  */
USI m32r2f_h_pc_get (SIM_CPU *);
void m32r2f_h_pc_set (SIM_CPU *, USI);
SI m32r2f_h_gr_get (SIM_CPU *, UINT);
void m32r2f_h_gr_set (SIM_CPU *, UINT, SI);
USI m32r2f_h_cr_get (SIM_CPU *, UINT);
void m32r2f_h_cr_set (SIM_CPU *, UINT, USI);
DI m32r2f_h_accum_get (SIM_CPU *);
void m32r2f_h_accum_set (SIM_CPU *, DI);
DI m32r2f_h_accums_get (SIM_CPU *, UINT);
void m32r2f_h_accums_set (SIM_CPU *, UINT, DI);
BI m32r2f_h_cond_get (SIM_CPU *);
void m32r2f_h_cond_set (SIM_CPU *, BI);
UQI m32r2f_h_psw_get (SIM_CPU *);
void m32r2f_h_psw_set (SIM_CPU *, UQI);
UQI m32r2f_h_bpsw_get (SIM_CPU *);
void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
UQI m32r2f_h_bbpsw_get (SIM_CPU *);
void m32r2f_h_bbpsw_set (SIM_CPU *, UQI);
BI m32r2f_h_lock_get (SIM_CPU *);
void m32r2f_h_lock_set (SIM_CPU *, BI);

/* These must be hand-written.  */
extern CPUREG_FETCH_FN m32r2f_fetch_register;
extern CPUREG_STORE_FN m32r2f_store_register;

typedef struct {
  int empty;
} MODEL_M32R2_DATA;

/* Instruction argument buffer.  */

union sem_fields {
  struct { /* no operands */
    int empty;
  } sfmt_empty;
  struct { /*  */
    UINT f_uimm8;
  } sfmt_clrpsw;
  struct { /*  */
    UINT f_uimm4;
  } sfmt_trap;
  struct { /*  */
    IADDR i_disp24;
    unsigned char out_h_gr_SI_14;
  } sfmt_bl24;
  struct { /*  */
    IADDR i_disp8;
    unsigned char out_h_gr_SI_14;
  } sfmt_bl8;
  struct { /*  */
    SI f_imm1;
    UINT f_accd;
    UINT f_accs;
  } sfmt_rac_dsi;
  struct { /*  */
    SI* i_dr;
    UINT f_hi16;
    UINT f_r1;
    unsigned char out_dr;
  } sfmt_seth;
  struct { /*  */
    SI* i_src1;
    UINT f_accs;
    UINT f_r1;
    unsigned char in_src1;
  } sfmt_mvtachi_a;
  struct { /*  */
    SI* i_dr;
    UINT f_accs;
    UINT f_r1;
    unsigned char out_dr;
  } sfmt_mvfachi_a;
  struct { /*  */
    ADDR i_uimm24;
    SI* i_dr;
    UINT f_r1;
    unsigned char out_dr;
  } sfmt_ld24;
  struct { /*  */
    SI* i_sr;
    UINT f_r2;
    unsigned char in_sr;
    unsigned char out_h_gr_SI_14;
  } sfmt_jl;
  struct { /*  */
    SI* i_sr;
    INT f_simm16;
    UINT f_r2;
    UINT f_uimm3;
    unsigned char in_sr;
  } sfmt_bset;
  struct { /*  */
    SI* i_dr;
    UINT f_r1;
    UINT f_uimm5;
    unsigned char in_dr;
    unsigned char out_dr;
  } sfmt_slli;
  struct { /*  */
    SI* i_dr;
    INT f_simm8;
    UINT f_r1;
    unsigned char in_dr;
    unsigned char out_dr;
  } sfmt_addi;
  struct { /*  */
    SI* i_src1;
    SI* i_src2;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_src1;
    unsigned char in_src2;
    unsigned char out_src2;
  } sfmt_st_plus;
  struct { /*  */
    SI* i_src1;
    SI* i_src2;
    INT f_simm16;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_src1;
    unsigned char in_src2;
  } sfmt_st_d;
  struct { /*  */
    SI* i_src1;
    SI* i_src2;
    UINT f_acc;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_src1;
    unsigned char in_src2;
  } sfmt_machi_a;
  struct { /*  */
    SI* i_dr;
    SI* i_sr;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_sr;
    unsigned char out_dr;
    unsigned char out_sr;
  } sfmt_ld_plus;
  struct { /*  */
    IADDR i_disp16;
    SI* i_src1;
    SI* i_src2;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_src1;
    unsigned char in_src2;
  } sfmt_beq;
  struct { /*  */
    SI* i_dr;
    SI* i_sr;
    UINT f_r1;
    UINT f_r2;
    UINT f_uimm16;
    unsigned char in_sr;
    unsigned char out_dr;
  } sfmt_and3;
  struct { /*  */
    SI* i_dr;
    SI* i_sr;
    INT f_simm16;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_sr;
    unsigned char out_dr;
  } sfmt_add3;
  struct { /*  */
    SI* i_dr;
    SI* i_sr;
    UINT f_r1;
    UINT f_r2;
    unsigned char in_dr;
    unsigned char in_sr;
    unsigned char out_dr;
  } sfmt_add;
#if WITH_SCACHE_PBB
  /* Writeback handler.  */
  struct {
    /* Pointer to argbuf entry for insn whose results need writing back.  */
    const struct argbuf *abuf;
  } write;
  /* x-before handler */
  struct {
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
    int first_p;
  } before;
  /* x-after handler */
  struct {
    int empty;
  } after;
  /* This entry is used to terminate each pbb.  */
  struct {
    /* Number of insns in pbb.  */
    int insn_count;
    /* Next pbb to execute.  */
    SCACHE *next;
    SCACHE *branch_target;
  } chain;
#endif
};

/* The ARGBUF struct.  */
struct argbuf {
  /* These are the baseclass definitions.  */
  IADDR addr;
  const IDESC *idesc;
  char trace_p;
  char profile_p;
  /* ??? Temporary hack for skip insns.  */
  char skip_count;
  char unused;
  /* cpu specific data follows */
  union sem semantic;
  int written;
  union sem_fields fields;
};

/* A cached insn.

   ??? SCACHE used to contain more than just argbuf.  We could delete the
   type entirely and always just use ARGBUF, but for future concerns and as
   a level of abstraction it is left in.  */

struct scache {
  struct argbuf argbuf;
};

/* Macros to simplify extraction, reading and semantic code.
   These define and assign the local vars that contain the insn's fields.  */

#define EXTRACT_IFMT_EMPTY_VARS \
  unsigned int length;
#define EXTRACT_IFMT_EMPTY_CODE \
  length = 0; \

#define EXTRACT_IFMT_ADD_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_ADD_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_ADD3_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_ADD3_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_AND3_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  UINT f_uimm16; \
  unsigned int length;
#define EXTRACT_IFMT_AND3_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_OR3_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  UINT f_uimm16; \
  unsigned int length;
#define EXTRACT_IFMT_OR3_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_ADDI_VARS \
  UINT f_op1; \
  UINT f_r1; \
  INT f_simm8; \
  unsigned int length;
#define EXTRACT_IFMT_ADDI_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \

#define EXTRACT_IFMT_ADDV3_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_ADDV3_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_BC8_VARS \
  UINT f_op1; \
  UINT f_r1; \
  SI f_disp8; \
  unsigned int length;
#define EXTRACT_IFMT_BC8_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \

#define EXTRACT_IFMT_BC24_VARS \
  UINT f_op1; \
  UINT f_r1; \
  SI f_disp24; \
  unsigned int length;
#define EXTRACT_IFMT_BC24_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \

#define EXTRACT_IFMT_BEQ_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  SI f_disp16; \
  unsigned int length;
#define EXTRACT_IFMT_BEQ_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \

#define EXTRACT_IFMT_BEQZ_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  SI f_disp16; \
  unsigned int length;
#define EXTRACT_IFMT_BEQZ_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \

#define EXTRACT_IFMT_CMP_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_CMP_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_CMPI_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_CMPI_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_CMPZ_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_CMPZ_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_DIV_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_DIV_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_JC_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_JC_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_LD24_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_uimm24; \
  unsigned int length;
#define EXTRACT_IFMT_LD24_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \

#define EXTRACT_IFMT_LDI16_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_LDI16_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_MACHI_A_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_acc; \
  UINT f_op23; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_MACHI_A_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_MVFACHI_A_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_accs; \
  UINT f_op3; \
  unsigned int length;
#define EXTRACT_IFMT_MVFACHI_A_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \

#define EXTRACT_IFMT_MVFC_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_MVFC_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_MVTACHI_A_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_accs; \
  UINT f_op3; \
  unsigned int length;
#define EXTRACT_IFMT_MVTACHI_A_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \

#define EXTRACT_IFMT_MVTC_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_MVTC_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_NOP_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_NOP_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_RAC_DSI_VARS \
  UINT f_op1; \
  UINT f_accd; \
  UINT f_bits67; \
  UINT f_op2; \
  UINT f_accs; \
  UINT f_bit14; \
  SI f_imm1; \
  unsigned int length;
#define EXTRACT_IFMT_RAC_DSI_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \

#define EXTRACT_IFMT_SETH_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  UINT f_hi16; \
  unsigned int length;
#define EXTRACT_IFMT_SETH_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_SLLI_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_shift_op2; \
  UINT f_uimm5; \
  unsigned int length;
#define EXTRACT_IFMT_SLLI_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \

#define EXTRACT_IFMT_ST_D_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_ST_D_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_TRAP_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_uimm4; \
  unsigned int length;
#define EXTRACT_IFMT_TRAP_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

#define EXTRACT_IFMT_SATB_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_op2; \
  UINT f_r2; \
  UINT f_uimm16; \
  unsigned int length;
#define EXTRACT_IFMT_SATB_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_CLRPSW_VARS \
  UINT f_op1; \
  UINT f_r1; \
  UINT f_uimm8; \
  unsigned int length;
#define EXTRACT_IFMT_CLRPSW_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \

#define EXTRACT_IFMT_BSET_VARS \
  UINT f_op1; \
  UINT f_bit4; \
  UINT f_uimm3; \
  UINT f_op2; \
  UINT f_r2; \
  INT f_simm16; \
  unsigned int length;
#define EXTRACT_IFMT_BSET_CODE \
  length = 4; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \

#define EXTRACT_IFMT_BTST_VARS \
  UINT f_op1; \
  UINT f_bit4; \
  UINT f_uimm3; \
  UINT f_op2; \
  UINT f_r2; \
  unsigned int length;
#define EXTRACT_IFMT_BTST_CODE \
  length = 2; \
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \

/* Queued output values of an instruction.  */

struct parexec {
  union {
    struct { /* empty sformat for unspecified field list */
      int empty;
    } sfmt_empty;
    struct { /* e.g. add $dr,$sr */
      SI dr;
    } sfmt_add;
    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
      SI dr;
    } sfmt_add3;
    struct { /* e.g. and3 $dr,$sr,$uimm16 */
      SI dr;
    } sfmt_and3;
    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
      SI dr;
    } sfmt_or3;
    struct { /* e.g. addi $dr,$simm8 */
      SI dr;
    } sfmt_addi;
    struct { /* e.g. addv $dr,$sr */
      BI condbit;
      SI dr;
    } sfmt_addv;
    struct { /* e.g. addv3 $dr,$sr,$simm16 */
      BI condbit;
      SI dr;
    } sfmt_addv3;
    struct { /* e.g. addx $dr,$sr */
      BI condbit;
      SI dr;
    } sfmt_addx;
    struct { /* e.g. bc.s $disp8 */
      USI pc;
    } sfmt_bc8;
    struct { /* e.g. bc.l $disp24 */
      USI pc;
    } sfmt_bc24;
    struct { /* e.g. beq $src1,$src2,$disp16 */
      USI pc;
    } sfmt_beq;
    struct { /* e.g. beqz $src2,$disp16 */
      USI pc;
    } sfmt_beqz;
    struct { /* e.g. bl.s $disp8 */
      SI h_gr_SI_14;
      USI pc;
    } sfmt_bl8;
    struct { /* e.g. bl.l $disp24 */
      SI h_gr_SI_14;
      USI pc;
    } sfmt_bl24;
    struct { /* e.g. bcl.s $disp8 */
      SI h_gr_SI_14;
      USI pc;
    } sfmt_bcl8;
    struct { /* e.g. bcl.l $disp24 */
      SI h_gr_SI_14;
      USI pc;
    } sfmt_bcl24;
    struct { /* e.g. bra.s $disp8 */
      USI pc;
    } sfmt_bra8;
    struct { /* e.g. bra.l $disp24 */
      USI pc;
    } sfmt_bra24;
    struct { /* e.g. cmp $src1,$src2 */
      BI condbit;
    } sfmt_cmp;
    struct { /* e.g. cmpi $src2,$simm16 */
      BI condbit;
    } sfmt_cmpi;
    struct { /* e.g. cmpz $src2 */
      BI condbit;
    } sfmt_cmpz;
    struct { /* e.g. div $dr,$sr */
      SI dr;
    } sfmt_div;
    struct { /* e.g. jc $sr */
      USI pc;
    } sfmt_jc;
    struct { /* e.g. jl $sr */
      SI h_gr_SI_14;
      USI pc;
    } sfmt_jl;
    struct { /* e.g. jmp $sr */
      USI pc;
    } sfmt_jmp;
    struct { /* e.g. ld $dr,@$sr */
      SI dr;
    } sfmt_ld;
    struct { /* e.g. ld $dr,@($slo16,$sr) */
      SI dr;
    } sfmt_ld_d;
    struct { /* e.g. ldb $dr,@$sr */
      SI dr;
    } sfmt_ldb;
    struct { /* e.g. ldb $dr,@($slo16,$sr) */
      SI dr;
    } sfmt_ldb_d;
    struct { /* e.g. ldh $dr,@$sr */
      SI dr;
    } sfmt_ldh;
    struct { /* e.g. ldh $dr,@($slo16,$sr) */
      SI dr;
    } sfmt_ldh_d;
    struct { /* e.g. ld $dr,@$sr+ */
      SI dr;
      SI sr;
    } sfmt_ld_plus;
    struct { /* e.g. ld24 $dr,$uimm24 */
      SI dr;
    } sfmt_ld24;
    struct { /* e.g. ldi8 $dr,$simm8 */
      SI dr;
    } sfmt_ldi8;
    struct { /* e.g. ldi16 $dr,$hash$slo16 */
      SI dr;
    } sfmt_ldi16;
    struct { /* e.g. lock $dr,@$sr */
      SI dr;
      BI h_lock_BI;
    } sfmt_lock;
    struct { /* e.g. machi $src1,$src2,$acc */
      DI acc;
    } sfmt_machi_a;
    struct { /* e.g. mulhi $src1,$src2,$acc */
      DI acc;
    } sfmt_mulhi_a;
    struct { /* e.g. mv $dr,$sr */
      SI dr;
    } sfmt_mv;
    struct { /* e.g. mvfachi $dr,$accs */
      SI dr;
    } sfmt_mvfachi_a;
    struct { /* e.g. mvfc $dr,$scr */
      SI dr;
    } sfmt_mvfc;
    struct { /* e.g. mvtachi $src1,$accs */
      DI accs;
    } sfmt_mvtachi_a;
    struct { /* e.g. mvtc $sr,$dcr */
      USI dcr;
    } sfmt_mvtc;
    struct { /* e.g. nop */
      int empty;
    } sfmt_nop;
    struct { /* e.g. rac $accd,$accs,$imm1 */
      DI accd;
    } sfmt_rac_dsi;
    struct { /* e.g. rte */
      UQI h_bpsw_UQI;
      USI h_cr_USI_6;
      UQI h_psw_UQI;
      USI pc;
    } sfmt_rte;
    struct { /* e.g. seth $dr,$hash$hi16 */
      SI dr;
    } sfmt_seth;
    struct { /* e.g. sll3 $dr,$sr,$simm16 */
      SI dr;
    } sfmt_sll3;
    struct { /* e.g. slli $dr,$uimm5 */
      SI dr;
    } sfmt_slli;
    struct { /* e.g. st $src1,@$src2 */
      SI h_memory_SI_src2;
      USI h_memory_SI_src2_idx;
    } sfmt_st;
    struct { /* e.g. st $src1,@($slo16,$src2) */
      SI h_memory_SI_add__SI_src2_slo16;
      USI h_memory_SI_add__SI_src2_slo16_idx;
    } sfmt_st_d;
    struct { /* e.g. stb $src1,@$src2 */
      QI h_memory_QI_src2;
      USI h_memory_QI_src2_idx;
    } sfmt_stb;
    struct { /* e.g. stb $src1,@($slo16,$src2) */
      QI h_memory_QI_add__SI_src2_slo16;
      USI h_memory_QI_add__SI_src2_slo16_idx;
    } sfmt_stb_d;
    struct { /* e.g. sth $src1,@$src2 */
      HI h_memory_HI_src2;
      USI h_memory_HI_src2_idx;
    } sfmt_sth;
    struct { /* e.g. sth $src1,@($slo16,$src2) */
      HI h_memory_HI_add__SI_src2_slo16;
      USI h_memory_HI_add__SI_src2_slo16_idx;
    } sfmt_sth_d;
    struct { /* e.g. st $src1,@+$src2 */
      SI h_memory_SI_new_src2;
      USI h_memory_SI_new_src2_idx;
      SI src2;
    } sfmt_st_plus;
    struct { /* e.g. sth $src1,@$src2+ */
      HI h_memory_HI_new_src2;
      USI h_memory_HI_new_src2_idx;
      SI src2;
    } sfmt_sth_plus;
    struct { /* e.g. stb $src1,@$src2+ */
      QI h_memory_QI_new_src2;
      USI h_memory_QI_new_src2_idx;
      SI src2;
    } sfmt_stb_plus;
    struct { /* e.g. trap $uimm4 */
      UQI h_bbpsw_UQI;
      UQI h_bpsw_UQI;
      USI h_cr_USI_14;
      USI h_cr_USI_6;
      UQI h_psw_UQI;
      USI pc;
    } sfmt_trap;
    struct { /* e.g. unlock $src1,@$src2 */
      BI h_lock_BI;
      SI h_memory_SI_src2;
      USI h_memory_SI_src2_idx;
    } sfmt_unlock;
    struct { /* e.g. satb $dr,$sr */
      SI dr;
    } sfmt_satb;
    struct { /* e.g. sat $dr,$sr */
      SI dr;
    } sfmt_sat;
    struct { /* e.g. sadd */
      DI h_accums_DI_0;
    } sfmt_sadd;
    struct { /* e.g. macwu1 $src1,$src2 */
      DI h_accums_DI_1;
    } sfmt_macwu1;
    struct { /* e.g. msblo $src1,$src2 */
      DI accum;
    } sfmt_msblo;
    struct { /* e.g. mulwu1 $src1,$src2 */
      DI h_accums_DI_1;
    } sfmt_mulwu1;
    struct { /* e.g. sc */
      int empty;
    } sfmt_sc;
    struct { /* e.g. clrpsw $uimm8 */
      USI h_cr_USI_0;
    } sfmt_clrpsw;
    struct { /* e.g. setpsw $uimm8 */
      USI h_cr_USI_0;
    } sfmt_setpsw;
    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
      QI h_memory_QI_add__SI_sr_slo16;
      USI h_memory_QI_add__SI_sr_slo16_idx;
    } sfmt_bset;
    struct { /* e.g. btst $uimm3,$sr */
      BI condbit;
    } sfmt_btst;
  } operands;
  /* For conditionally written operands, bitmask of which ones were.  */
  int written;
};

/* Collection of various things for the trace handler to use.  */

typedef struct trace_record {
  IADDR pc;
  /* FIXME:wip */
} TRACE_RECORD;

#endif /* CPU_M32R2F_H */