blob: f86f658cbef6cf4c520608227c775e2253cb0b76 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
/* sim-main.h -- Interface with sim/common.
Copyright (C) 2015-2016 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H
#include "sim-basics.h"
#include "sim-types.h"
#include "sim-base.h"
#include "sim-base.h"
#include "sim-io.h"
#include "cpustate.h"
/* A per-core state structure. */
struct _sim_cpu
{
GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
FRegister fr[32];
uint64_t pc;
uint32_t CPSR;
uint32_t FPSR; /* Floating point Status register. */
uint32_t FPCR; /* Floating point Control register. */
uint64_t nextpc;
uint32_t instr;
uint64_t tpidr; /* Thread pointer id. */
sim_cpu_base base;
};
typedef enum
{
AARCH64_MIN_GR = 0,
AARCH64_MAX_GR = 31,
AARCH64_MIN_FR = 32,
AARCH64_MAX_FR = 63,
AARCH64_PC_REGNO = 64,
AARCH64_CPSR_REGNO = 65,
AARCH64_FPSR_REGNO = 66,
AARCH64_MAX_REGNO = 67
} aarch64_regno;
/* The simulator state structure used to hold all global variables. */
struct sim_state
{
sim_cpu * cpu[MAX_NR_PROCESSORS];
sim_state_base base;
};
#endif /* _SIM_MAIN_H */
|