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<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>riscv</architecture>
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="zero" bitsize="32" type="int"/>
<reg name="ra" bitsize="32" type="code_ptr"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="gp" bitsize="32" type="data_ptr"/>
<reg name="tp" bitsize="32" type="data_ptr"/>
<reg name="t0" bitsize="32" type="int"/>
<reg name="t1" bitsize="32" type="int"/>
<reg name="t2" bitsize="32" type="int"/>
<reg name="fp" bitsize="32" type="data_ptr"/>
<reg name="s1" bitsize="32" type="int"/>
<reg name="a0" bitsize="32" type="int"/>
<reg name="a1" bitsize="32" type="int"/>
<reg name="a2" bitsize="32" type="int"/>
<reg name="a3" bitsize="32" type="int"/>
<reg name="a4" bitsize="32" type="int"/>
<reg name="a5" bitsize="32" type="int"/>
<reg name="a6" bitsize="32" type="int"/>
<reg name="a7" bitsize="32" type="int"/>
<reg name="s2" bitsize="32" type="int"/>
<reg name="s3" bitsize="32" type="int"/>
<reg name="s4" bitsize="32" type="int"/>
<reg name="s5" bitsize="32" type="int"/>
<reg name="s6" bitsize="32" type="int"/>
<reg name="s7" bitsize="32" type="int"/>
<reg name="s8" bitsize="32" type="int"/>
<reg name="s9" bitsize="32" type="int"/>
<reg name="s10" bitsize="32" type="int"/>
<reg name="s11" bitsize="32" type="int"/>
<reg name="t3" bitsize="32" type="int"/>
<reg name="t4" bitsize="32" type="int"/>
<reg name="t5" bitsize="32" type="int"/>
<reg name="t6" bitsize="32" type="int"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
</feature>
<feature name="org.gnu.gdb.riscv.fpu">
<reg name="ft0" bitsize="32" type="float"/>
<reg name="ft1" bitsize="32" type="float"/>
<reg name="ft2" bitsize="32" type="float"/>
<reg name="ft3" bitsize="32" type="float"/>
<reg name="ft4" bitsize="32" type="float"/>
<reg name="ft5" bitsize="32" type="float"/>
<reg name="ft6" bitsize="32" type="float"/>
<reg name="ft7" bitsize="32" type="float"/>
<reg name="fs0" bitsize="32" type="float"/>
<reg name="fs1" bitsize="32" type="float"/>
<reg name="fa0" bitsize="32" type="float"/>
<reg name="fa1" bitsize="32" type="float"/>
<reg name="fa2" bitsize="32" type="float"/>
<reg name="fa3" bitsize="32" type="float"/>
<reg name="fa4" bitsize="32" type="float"/>
<reg name="fa5" bitsize="32" type="float"/>
<reg name="fa6" bitsize="32" type="float"/>
<reg name="fa7" bitsize="32" type="float"/>
<reg name="fs2" bitsize="32" type="float"/>
<reg name="fs3" bitsize="32" type="float"/>
<reg name="fs4" bitsize="32" type="float"/>
<reg name="fs5" bitsize="32" type="float"/>
<reg name="fs6" bitsize="32" type="float"/>
<reg name="fs7" bitsize="32" type="float"/>
<reg name="fs8" bitsize="32" type="float"/>
<reg name="fs9" bitsize="32" type="float"/>
<reg name="fs10" bitsize="32" type="float"/>
<reg name="fs11" bitsize="32" type="float"/>
<reg name="ft8" bitsize="32" type="float"/>
<reg name="ft9" bitsize="32" type="float"/>
<reg name="ft10" bitsize="32" type="float"/>
<reg name="ft11" bitsize="32" type="float"/>
<!-- The following 3 registers are duplicated. -->
<reg name="fflags" bitsize="32" type="int"/>
<reg name="frm" bitsize="32" type="int"/>
<reg name="fcsr" bitsize="32" type="int"/>
</feature>
<feature name="org.gnu.gdb.riscv.csr">
<!-- The following 3 registers are duplicated. -->
<reg name="fflags" bitsize="32" type="int"/>
<reg name="frm" bitsize="32" type="int"/>
<reg name="fcsr" bitsize="32" type="int"/>
<!-- The following is a CSR unknown to GDB. -->
<reg name="unknown_csr" bitsize="32" type="int"/>
<!-- The following is now known as 'dscratch0' in the official
RISC-V spec, but GDB should NOT rename this register. -->
<reg name="dscratch" bitsize="32" type="int"/>
</feature>
</target>
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