aboutsummaryrefslogtreecommitdiff
path: root/gdb/sh-tdep.c
blob: fbc5c9f1d0dfb4e3afe9f54e2445bc02fdb4194a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
/* Target-dependent code for Renesas Super-H, for GDB.

   Copyright (C) 1993-2018 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* Contributed by Steve Chamberlain
   sac@cygnus.com.  */

#include "defs.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "dwarf2-frame.h"
#include "symtab.h"
#include "gdbtypes.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "value.h"
#include "dis-asm.h"
#include "inferior.h"
#include "arch-utils.h"
#include "regcache.h"
#include "target-float.h"
#include "osabi.h"
#include "reggroups.h"
#include "regset.h"
#include "objfiles.h"

#include "sh-tdep.h"
#include "sh64-tdep.h"

#include "elf-bfd.h"
#include "solib-svr4.h"

/* sh flags */
#include "elf/sh.h"
#include "dwarf2.h"
/* registers numbers shared with the simulator.  */
#include "gdb/sim-sh.h"
#include <algorithm>

/* List of "set sh ..." and "show sh ..." commands.  */
static struct cmd_list_element *setshcmdlist = NULL;
static struct cmd_list_element *showshcmdlist = NULL;

static const char sh_cc_gcc[] = "gcc";
static const char sh_cc_renesas[] = "renesas";
static const char *const sh_cc_enum[] = {
  sh_cc_gcc,
  sh_cc_renesas, 
  NULL
};

static const char *sh_active_calling_convention = sh_cc_gcc;

#define SH_NUM_REGS 67

struct sh_frame_cache
{
  /* Base address.  */
  CORE_ADDR base;
  LONGEST sp_offset;
  CORE_ADDR pc;

  /* Flag showing that a frame has been created in the prologue code.  */
  int uses_fp;

  /* Saved registers.  */
  CORE_ADDR saved_regs[SH_NUM_REGS];
  CORE_ADDR saved_sp;
};

static int
sh_is_renesas_calling_convention (struct type *func_type)
{
  int val = 0;

  if (func_type)
    {
      func_type = check_typedef (func_type);

      if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
        func_type = check_typedef (TYPE_TARGET_TYPE (func_type));

      if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
          && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
        val = 1;
    }

  if (sh_active_calling_convention == sh_cc_renesas)
    val = 1;

  return val;
}

static const char *
sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    "ssr", "spc",
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "fpul", "fpscr",
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
    "ssr", "spc",
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "fpul", "fpscr",
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
    "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    /* general registers 0-15 */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    /* 16 - 22 */
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    /* 23, 24 */
    "fpul", "fpscr",
    /* floating point registers 25 - 40 */
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
    /* 41, 42 */
    "", "",
    /* 43 - 62.  Banked registers.  The bank number used is determined by
       the bank register (63).  */
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
    "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
    "machb", "ivnb", "prb", "gbrb", "maclb",
    /* 63: register bank number, not a real register but used to
       communicate the register bank currently get/set.  This register
       is hidden to the user, who manipulates it using the pseudo
       register called "bank" (67).  See below.  */
    "",
    /* 64 - 66 */
    "ibcr", "ibnr", "tbr",
    /* 67: register bank number, the user visible pseudo register.  */
    "bank",
    /* double precision (pseudo) 68 - 75 */
    "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    /* general registers 0-15 */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    /* 16 - 22 */
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    /* 23, 24 */
    "", "",
    /* floating point registers 25 - 40 */
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    /* 41, 42 */
    "", "",
    /* 43 - 62.  Banked registers.  The bank number used is determined by
       the bank register (63).  */
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
    "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
    "machb", "ivnb", "prb", "gbrb", "maclb",
    /* 63: register bank number, not a real register but used to
       communicate the register bank currently get/set.  This register
       is hidden to the user, who manipulates it using the pseudo
       register called "bank" (67).  See below.  */
    "",
    /* 64 - 66 */
    "ibcr", "ibnr", "tbr",
    /* 67: register bank number, the user visible pseudo register.  */
    "bank",
    /* double precision (pseudo) 68 - 75 */
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "", "dsr",
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
    "y0", "y1", "", "", "", "", "", "mod",
    "", "",
    "rs", "re", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "", "dsr",
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
    "y0", "y1", "", "", "", "", "", "mod",
    "ssr", "spc",
    "rs", "re", "", "", "", "", "", "",
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    /* general registers 0-15 */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    /* 16 - 22 */
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    /* 23, 24 */
    "fpul", "fpscr",
    /* floating point registers 25 - 40 */
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
    /* 41, 42 */
    "ssr", "spc",
    /* bank 0 43 - 50 */
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
    /* bank 1 51 - 58 */
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
    /* 59 - 66 */
    "", "", "", "", "", "", "", "",
    /* pseudo bank register.  */
    "",
    /* double precision (pseudo) 68 - 75 */
    "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
    /* vectors (pseudo) 76 - 79 */
    "fv0", "fv4", "fv8", "fv12",
    /* FIXME: missing XF */
    /* FIXME: missing XD */
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    /* general registers 0-15 */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    /* 16 - 22 */
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    /* 23, 24 */
    "", "",
    /* floating point registers 25 - 40 -- not for nofpu target */
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
    /* 41, 42 */
    "ssr", "spc",
    /* bank 0 43 - 50 */
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
    /* bank 1 51 - 58 */
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
    /* 59 - 66 */
    "", "", "", "", "", "", "", "",
    /* pseudo bank register.  */
    "",
    /* double precision (pseudo) 68 - 75 -- not for nofpu target */
    "", "", "", "", "", "", "", "",
    /* vectors (pseudo) 76 - 79 -- not for nofpu target */
    "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

static const char *
sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static const char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
    "", "dsr",
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
    "y0", "y1", "", "", "", "", "", "mod",
    "ssr", "spc",
    "rs", "re", "", "", "", "", "", "",
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
    "", "", "", "", "", "", "", "",
    "", "", "", "", "", "", "", "",
  };
  if (reg_nr < 0)
    return NULL;
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
    return NULL;
  return register_names[reg_nr];
}

/* Implement the breakpoint_kind_from_pc gdbarch method.  */

static int
sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
{
  return 2;
}

/* Implement the sw_breakpoint_from_kind gdbarch method.  */

static const gdb_byte *
sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
{
  *size = kind;

  /* For remote stub targets, trapa #20 is used.  */
  if (strcmp (target_shortname, "remote") == 0)
    {
      static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
      static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };

      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
	return big_remote_breakpoint;
      else
	return little_remote_breakpoint;
    }
  else
    {
      /* 0xc3c3 is trapa #c3, and it works in big and little endian
	 modes.  */
      static unsigned char breakpoint[] = { 0xc3, 0xc3 };

      return breakpoint;
    }
}

/* Prologue looks like
   mov.l	r14,@-r15
   sts.l	pr,@-r15
   mov.l	<regs>,@-r15
   sub		<room_for_loca_vars>,r15
   mov		r15,r14

   Actually it can be more complicated than this but that's it, basically.  */

#define GET_SOURCE_REG(x)  	(((x) >> 4) & 0xf)
#define GET_TARGET_REG(x)  	(((x) >> 8) & 0xf)

/* JSR @Rm         0100mmmm00001011 */
#define IS_JSR(x)		(((x) & 0xf0ff) == 0x400b)

/* STS.L PR,@-r15  0100111100100010
   r15-4-->r15, PR-->(r15) */
#define IS_STS(x)  		((x) == 0x4f22)

/* STS.L MACL,@-r15  0100111100010010
   r15-4-->r15, MACL-->(r15) */
#define IS_MACL_STS(x)  	((x) == 0x4f12)

/* MOV.L Rm,@-r15  00101111mmmm0110
   r15-4-->r15, Rm-->(R15) */
#define IS_PUSH(x) 		(((x) & 0xff0f) == 0x2f06)

/* MOV r15,r14     0110111011110011
   r15-->r14  */
#define IS_MOV_SP_FP(x)  	((x) == 0x6ef3)

/* ADD #imm,r15    01111111iiiiiiii
   r15+imm-->r15 */
#define IS_ADD_IMM_SP(x) 	(((x) & 0xff00) == 0x7f00)

#define IS_MOV_R3(x) 		(((x) & 0xff00) == 0x1a00)
#define IS_SHLL_R3(x)		((x) == 0x4300)

/* ADD r3,r15      0011111100111100
   r15+r3-->r15 */
#define IS_ADD_R3SP(x)		((x) == 0x3f3c)

/* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
   FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
   FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
		   make this entirely clear.  */
/* #define IS_FMOV(x)		(((x) & 0xf00f) == 0xf00b) */
#define IS_FPUSH(x)		(((x) & 0xff0f) == 0xff0b)

/* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
#define IS_MOV_ARG_TO_REG(x) \
	(((x) & 0xf00f) == 0x6003 && \
	 ((x) & 0x00f0) >= 0x0040 && \
	 ((x) & 0x00f0) <= 0x0070)
/* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
#define IS_MOV_ARG_TO_IND_R14(x) \
	(((x) & 0xff0f) == 0x2e02 && \
	 ((x) & 0x00f0) >= 0x0040 && \
	 ((x) & 0x00f0) <= 0x0070)
/* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
	(((x) & 0xff00) == 0x1e00 && \
	 ((x) & 0x00f0) >= 0x0040 && \
	 ((x) & 0x00f0) <= 0x0070)

/* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
#define IS_MOVW_PCREL_TO_REG(x)	(((x) & 0xf000) == 0x9000)
/* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
#define IS_MOVL_PCREL_TO_REG(x)	(((x) & 0xf000) == 0xd000)
/* MOVI20 #imm20,Rn           0000nnnniiii0000 */
#define IS_MOVI20(x)		(((x) & 0xf00f) == 0x0000)
/* SUB Rn,R15                 00111111nnnn1000 */
#define IS_SUB_REG_FROM_SP(x)	(((x) & 0xff0f) == 0x3f08)

#define FPSCR_SZ		(1 << 20)

/* The following instructions are used for epilogue testing.  */
#define IS_RESTORE_FP(x)	((x) == 0x6ef6)
#define IS_RTS(x)		((x) == 0x000b)
#define IS_LDS(x)  		((x) == 0x4f26)
#define IS_MACL_LDS(x)  	((x) == 0x4f16)
#define IS_MOV_FP_SP(x)  	((x) == 0x6fe3)
#define IS_ADD_REG_TO_FP(x)	(((x) & 0xff0f) == 0x3e0c)
#define IS_ADD_IMM_FP(x) 	(((x) & 0xff00) == 0x7e00)

static CORE_ADDR
sh_analyze_prologue (struct gdbarch *gdbarch,
		     CORE_ADDR pc, CORE_ADDR limit_pc,
		     struct sh_frame_cache *cache, ULONGEST fpscr)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  ULONGEST inst;
  int offset;
  int sav_offset = 0;
  int r3_val = 0;
  int reg, sav_reg = -1;

  cache->uses_fp = 0;
  for (; pc < limit_pc; pc += 2)
    {
      inst = read_memory_unsigned_integer (pc, 2, byte_order);
      /* See where the registers will be saved to.  */
      if (IS_PUSH (inst))
	{
	  cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
	  cache->sp_offset += 4;
	}
      else if (IS_STS (inst))
	{
	  cache->saved_regs[PR_REGNUM] = cache->sp_offset;
	  cache->sp_offset += 4;
	}
      else if (IS_MACL_STS (inst))
	{
	  cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
	  cache->sp_offset += 4;
	}
      else if (IS_MOV_R3 (inst))
	{
	  r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
	}
      else if (IS_SHLL_R3 (inst))
	{
	  r3_val <<= 1;
	}
      else if (IS_ADD_R3SP (inst))
	{
	  cache->sp_offset += -r3_val;
	}
      else if (IS_ADD_IMM_SP (inst))
	{
	  offset = ((inst & 0xff) ^ 0x80) - 0x80;
	  cache->sp_offset -= offset;
	}
      else if (IS_MOVW_PCREL_TO_REG (inst))
	{
	  if (sav_reg < 0)
	    {
	      reg = GET_TARGET_REG (inst);
	      if (reg < 14)
		{
		  sav_reg = reg;
		  offset = (inst & 0xff) << 1;
		  sav_offset =
		    read_memory_integer ((pc + 4) + offset, 2, byte_order);
		}
	    }
	}
      else if (IS_MOVL_PCREL_TO_REG (inst))
	{
	  if (sav_reg < 0)
	    {
	      reg = GET_TARGET_REG (inst);
	      if (reg < 14)
		{
		  sav_reg = reg;
		  offset = (inst & 0xff) << 2;
		  sav_offset =
		    read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
					 4, byte_order);
		}
	    }
	}
      else if (IS_MOVI20 (inst)
	       && (pc + 2 < limit_pc))
        {
	  if (sav_reg < 0)
	    {
	      reg = GET_TARGET_REG (inst);
	      if (reg < 14)
	        {
		  sav_reg = reg;
		  sav_offset = GET_SOURCE_REG (inst) << 16;
		  /* MOVI20 is a 32 bit instruction!  */
		  pc += 2;
		  sav_offset
		    |= read_memory_unsigned_integer (pc, 2, byte_order);
		  /* Now sav_offset contains an unsigned 20 bit value.
		     It must still get sign extended.  */
		  if (sav_offset & 0x00080000)
		    sav_offset |= 0xfff00000;
		}
	    }
	}
      else if (IS_SUB_REG_FROM_SP (inst))
	{
	  reg = GET_SOURCE_REG (inst);
	  if (sav_reg > 0 && reg == sav_reg)
	    {
	      sav_reg = -1;
	    }
	  cache->sp_offset += sav_offset;
	}
      else if (IS_FPUSH (inst))
	{
	  if (fpscr & FPSCR_SZ)
	    {
	      cache->sp_offset += 8;
	    }
	  else
	    {
	      cache->sp_offset += 4;
	    }
	}
      else if (IS_MOV_SP_FP (inst))
	{
	  pc += 2;
	  /* Don't go any further than six more instructions.  */
	  limit_pc = std::min (limit_pc, pc + (2 * 6));

	  cache->uses_fp = 1;
	  /* At this point, only allow argument register moves to other
	     registers or argument register moves to @(X,fp) which are
	     moving the register arguments onto the stack area allocated
	     by a former add somenumber to SP call.  Don't allow moving
	     to an fp indirect address above fp + cache->sp_offset.  */
	  for (; pc < limit_pc; pc += 2)
	    {
	      inst = read_memory_integer (pc, 2, byte_order);
	      if (IS_MOV_ARG_TO_IND_R14 (inst))
		{
		  reg = GET_SOURCE_REG (inst);
		  if (cache->sp_offset > 0)
		    cache->saved_regs[reg] = cache->sp_offset;
		}
	      else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
		{
		  reg = GET_SOURCE_REG (inst);
		  offset = (inst & 0xf) * 4;
		  if (cache->sp_offset > offset)
		    cache->saved_regs[reg] = cache->sp_offset - offset;
		}
	      else if (IS_MOV_ARG_TO_REG (inst))
		continue;
	      else
		break;
	    }
	  break;
	}
      else if (IS_JSR (inst))
	{
	  /* We have found a jsr that has been scheduled into the prologue.
	     If we continue the scan and return a pc someplace after this,
	     then setting a breakpoint on this function will cause it to
	     appear to be called after the function it is calling via the
	     jsr, which will be very confusing.  Most likely the next
	     instruction is going to be IS_MOV_SP_FP in the delay slot.  If
	     so, note that before returning the current pc.  */
	  if (pc + 2 < limit_pc)
	    {
	      inst = read_memory_integer (pc + 2, 2, byte_order);
	      if (IS_MOV_SP_FP (inst))
		cache->uses_fp = 1;
	    }
	  break;
	}
#if 0		/* This used to just stop when it found an instruction
		   that was not considered part of the prologue.  Now,
		   we just keep going looking for likely
		   instructions.  */
      else
	break;
#endif
    }

  return pc;
}

/* Skip any prologue before the guts of a function.  */
static CORE_ADDR
sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
  CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc;
  struct sh_frame_cache cache;

  /* See if we can determine the end of the prologue via the symbol table.
     If so, then return either PC, or the PC after the prologue, whichever
     is greater.  */
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
    {
      post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
      if (post_prologue_pc != 0)
        return std::max (pc, post_prologue_pc);
    }

  /* Can't determine prologue from the symbol table, need to examine
     instructions.  */

  /* Find an upper limit on the function prologue using the debug
     information.  If the debug information could not be used to provide
     that bound, then use an arbitrary large number as the upper bound.  */
  limit_pc = skip_prologue_using_sal (gdbarch, pc);
  if (limit_pc == 0)
    /* Don't go any further than 28 instructions.  */
    limit_pc = pc + (2 * 28);

  /* Do not allow limit_pc to be past the function end, if we know
     where that end is...  */
  if (func_end_addr != 0)
    limit_pc = std::min (limit_pc, func_end_addr);

  cache.sp_offset = -4;
  post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0);
  if (cache.uses_fp)
    pc = post_prologue_pc;

  return pc;
}

/* The ABI says:

   Aggregate types not bigger than 8 bytes that have the same size and
   alignment as one of the integer scalar types are returned in the
   same registers as the integer type they match.

   For example, a 2-byte aligned structure with size 2 bytes has the
   same size and alignment as a short int, and will be returned in R0.
   A 4-byte aligned structure with size 8 bytes has the same size and
   alignment as a long long int, and will be returned in R0 and R1.

   When an aggregate type is returned in R0 and R1, R0 contains the
   first four bytes of the aggregate, and R1 contains the
   remainder.  If the size of the aggregate type is not a multiple of 4
   bytes, the aggregate is tail-padded up to a multiple of 4
   bytes.  The value of the padding is undefined.  For little-endian
   targets the padding will appear at the most significant end of the
   last element, for big-endian targets the padding appears at the
   least significant end of the last element.

   All other aggregate types are returned by address.  The caller
   function passes the address of an area large enough to hold the
   aggregate value in R2.  The called function stores the result in
   this location.

   To reiterate, structs smaller than 8 bytes could also be returned
   in memory, if they don't pass the "same size and alignment as an
   integer type" rule.

   For example, in

   struct s { char c[3]; } wibble;
   struct s foo(void) {  return wibble; }

   the return value from foo() will be in memory, not
   in R0, because there is no 3-byte integer type.

   Similarly, in 

   struct s { char c[2]; } wibble;
   struct s foo(void) {  return wibble; }

   because a struct containing two chars has alignment 1, that matches
   type char, but size 2, that matches type short.  There's no integer
   type that has alignment 1 and size 2, so the struct is returned in
   memory.  */

static int
sh_use_struct_convention (int renesas_abi, struct type *type)
{
  int len = TYPE_LENGTH (type);
  int nelem = TYPE_NFIELDS (type);

  /* The Renesas ABI returns aggregate types always on stack.  */
  if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
		      || TYPE_CODE (type) == TYPE_CODE_UNION))
    return 1;

  /* Non-power of 2 length types and types bigger than 8 bytes (which don't
     fit in two registers anyway) use struct convention.  */
  if (len != 1 && len != 2 && len != 4 && len != 8)
    return 1;

  /* Scalar types and aggregate types with exactly one field are aligned
     by definition.  They are returned in registers.  */
  if (nelem <= 1)
    return 0;

  /* If the first field in the aggregate has the same length as the entire
     aggregate type, the type is returned in registers.  */
  if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
    return 0;

  /* If the size of the aggregate is 8 bytes and the first field is
     of size 4 bytes its alignment is equal to long long's alignment,
     so it's returned in registers.  */
  if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
    return 0;

  /* Otherwise use struct convention.  */
  return 1;
}

static int
sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
{
  /* The Renesas ABI returns long longs/doubles etc. always on stack.  */
  if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
    return 1;
  return sh_use_struct_convention (renesas_abi, type);
}

static CORE_ADDR
sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
{
  return sp & ~3;
}

/* Function: push_dummy_call (formerly push_arguments)
   Setup the function arguments for calling a function in the inferior.

   On the Renesas SH architecture, there are four registers (R4 to R7)
   which are dedicated for passing function arguments.  Up to the first
   four arguments (depending on size) may go into these registers.
   The rest go on the stack.

   MVS: Except on SH variants that have floating point registers.
   In that case, float and double arguments are passed in the same
   manner, but using FP registers instead of GP registers.

   Arguments that are smaller than 4 bytes will still take up a whole
   register or a whole 32-bit word on the stack, and will be 
   right-justified in the register or the stack word.  This includes
   chars, shorts, and small aggregate types.

   Arguments that are larger than 4 bytes may be split between two or 
   more registers.  If there are not enough registers free, an argument
   may be passed partly in a register (or registers), and partly on the
   stack.  This includes doubles, long longs, and larger aggregates.
   As far as I know, there is no upper limit to the size of aggregates 
   that will be passed in this way; in other words, the convention of 
   passing a pointer to a large aggregate instead of a copy is not used.

   MVS: The above appears to be true for the SH variants that do not
   have an FPU, however those that have an FPU appear to copy the
   aggregate argument onto the stack (and not place it in registers)
   if it is larger than 16 bytes (four GP registers).

   An exceptional case exists for struct arguments (and possibly other
   aggregates such as arrays) if the size is larger than 4 bytes but 
   not a multiple of 4 bytes.  In this case the argument is never split 
   between the registers and the stack, but instead is copied in its
   entirety onto the stack, AND also copied into as many registers as 
   there is room for.  In other words, space in registers permitting, 
   two copies of the same argument are passed in.  As far as I can tell,
   only the one on the stack is used, although that may be a function 
   of the level of compiler optimization.  I suspect this is a compiler
   bug.  Arguments of these odd sizes are left-justified within the 
   word (as opposed to arguments smaller than 4 bytes, which are 
   right-justified).

   If the function is to return an aggregate type such as a struct, it 
   is either returned in the normal return value register R0 (if its 
   size is no greater than one byte), or else the caller must allocate
   space into which the callee will copy the return value (if the size
   is greater than one byte).  In this case, a pointer to the return 
   value location is passed into the callee in register R2, which does 
   not displace any of the other arguments passed in via registers R4
   to R7.  */

/* Helper function to justify value in register according to endianess.  */
static const gdb_byte *
sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
{
  static gdb_byte valbuf[4];

  memset (valbuf, 0, sizeof (valbuf));
  if (len < 4)
    {
      /* value gets right-justified in the register or stack word.  */
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
	memcpy (valbuf + (4 - len), value_contents (val), len);
      else
	memcpy (valbuf, value_contents (val), len);
      return valbuf;
    }
  return value_contents (val);
}

/* Helper function to eval number of bytes to allocate on stack.  */
static CORE_ADDR
sh_stack_allocsize (int nargs, struct value **args)
{
  int stack_alloc = 0;
  while (nargs-- > 0)
    stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
  return stack_alloc;
}

/* Helper functions for getting the float arguments right.  Registers usage
   depends on the ABI and the endianess.  The comments should enlighten how
   it's intended to work.  */

/* This array stores which of the float arg registers are already in use.  */
static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];

/* This function just resets the above array to "no reg used so far".  */
static void
sh_init_flt_argreg (void)
{
  memset (flt_argreg_array, 0, sizeof flt_argreg_array);
}

/* This function returns the next register to use for float arg passing.
   It returns either a valid value between FLOAT_ARG0_REGNUM and
   FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns 
   FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.

   Note that register number 0 in flt_argreg_array corresponds with the
   real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
   29) the parity of the register number is preserved, which is important
   for the double register passing test (see the "argreg & 1" test below).  */
static int
sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
{
  int argreg;

  /* First search for the next free register.  */
  for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
       ++argreg)
    if (!flt_argreg_array[argreg])
      break;

  /* No register left?  */
  if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
    return FLOAT_ARGLAST_REGNUM + 1;

  if (len == 8)
    {
      /* Doubles are always starting in a even register number.  */
      if (argreg & 1)
	{
	  /* In gcc ABI, the skipped register is lost for further argument
	     passing now.  Not so in Renesas ABI.  */
	  if (!sh_is_renesas_calling_convention (func_type))
	    flt_argreg_array[argreg] = 1;

	  ++argreg;

	  /* No register left?  */
	  if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
	    return FLOAT_ARGLAST_REGNUM + 1;
	}
      /* Also mark the next register as used.  */
      flt_argreg_array[argreg + 1] = 1;
    }
  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
	   && !sh_is_renesas_calling_convention (func_type))
    {
      /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ...  */
      if (!flt_argreg_array[argreg + 1])
	++argreg;
    }
  flt_argreg_array[argreg] = 1;
  return FLOAT_ARG0_REGNUM + argreg;
}

/* Helper function which figures out, if a type is treated like a float type.

   The FPU ABIs have a special way how to treat types as float types.
   Structures with exactly one member, which is of type float or double, are
   treated exactly as the base types float or double:

     struct sf {
       float f;
     };

     struct sd {
       double d;
     };

   are handled the same way as just

     float f;

     double d;

   As a result, arguments of these struct types are pushed into floating point
   registers exactly as floats or doubles, using the same decision algorithm.

   The same is valid if these types are used as function return types.  The
   above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
   or even using struct convention as it is for other structs.  */

static int
sh_treat_as_flt_p (struct type *type)
{
  /* Ordinary float types are obviously treated as float.  */
  if (TYPE_CODE (type) == TYPE_CODE_FLT)
    return 1;
  /* Otherwise non-struct types are not treated as float.  */
  if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
    return 0;
  /* Otherwise structs with more than one memeber are not treated as float.  */
  if (TYPE_NFIELDS (type) != 1)
    return 0;
  /* Otherwise if the type of that member is float, the whole type is
     treated as float.  */
  if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
    return 1;
  /* Otherwise it's not treated as float.  */
  return 0;
}

static CORE_ADDR
sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
			struct value *function,
			struct regcache *regcache,
			CORE_ADDR bp_addr, int nargs,
			struct value **args,
			CORE_ADDR sp, int struct_return,
			CORE_ADDR struct_addr)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  int stack_offset = 0;
  int argreg = ARG0_REGNUM;
  int flt_argreg = 0;
  int argnum;
  struct type *func_type = value_type (function);
  struct type *type;
  CORE_ADDR regval;
  const gdb_byte *val;
  int len, reg_size = 0;
  int pass_on_stack = 0;
  int treat_as_flt;
  int last_reg_arg = INT_MAX;

  /* The Renesas ABI expects all varargs arguments, plus the last
     non-vararg argument to be on the stack, no matter how many
     registers have been used so far.  */
  if (sh_is_renesas_calling_convention (func_type)
      && TYPE_VARARGS (func_type))
    last_reg_arg = TYPE_NFIELDS (func_type) - 2;

  /* First force sp to a 4-byte alignment.  */
  sp = sh_frame_align (gdbarch, sp);

  /* Make room on stack for args.  */
  sp -= sh_stack_allocsize (nargs, args);

  /* Initialize float argument mechanism.  */
  sh_init_flt_argreg ();

  /* Now load as many as possible of the first arguments into
     registers, and push the rest onto the stack.  There are 16 bytes
     in four registers available.  Loop thru args from first to last.  */
  for (argnum = 0; argnum < nargs; argnum++)
    {
      type = value_type (args[argnum]);
      len = TYPE_LENGTH (type);
      val = sh_justify_value_in_reg (gdbarch, args[argnum], len);

      /* Some decisions have to be made how various types are handled.
         This also differs in different ABIs.  */
      pass_on_stack = 0;

      /* Find out the next register to use for a floating point value.  */
      treat_as_flt = sh_treat_as_flt_p (type);
      if (treat_as_flt)
	flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
      /* In Renesas ABI, long longs and aggregate types are always passed
	 on stack.  */
      else if (sh_is_renesas_calling_convention (func_type)
	       && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
		   || TYPE_CODE (type) == TYPE_CODE_STRUCT
		   || TYPE_CODE (type) == TYPE_CODE_UNION))
	pass_on_stack = 1;
      /* In contrast to non-FPU CPUs, arguments are never split between
	 registers and stack.  If an argument doesn't fit in the remaining
	 registers it's always pushed entirely on the stack.  */
      else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
	pass_on_stack = 1;

      while (len > 0)
	{
	  if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
	      || (!treat_as_flt && (argreg > ARGLAST_REGNUM
	                            || pass_on_stack))
	      || argnum > last_reg_arg)
	    {
	      /* The data goes entirely on the stack, 4-byte aligned.  */
	      reg_size = (len + 3) & ~3;
	      write_memory (sp + stack_offset, val, reg_size);
	      stack_offset += reg_size;
	    }
	  else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
	    {
	      /* Argument goes in a float argument register.  */
	      reg_size = register_size (gdbarch, flt_argreg);
	      regval = extract_unsigned_integer (val, reg_size, byte_order);
	      /* In little endian mode, float types taking two registers
	         (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
		 be stored swapped in the argument registers.  The below
		 code first writes the first 32 bits in the next but one
		 register, increments the val and len values accordingly
		 and then proceeds as normal by writing the second 32 bits
		 into the next register.  */
	      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
	          && TYPE_LENGTH (type) == 2 * reg_size)
	        {
		  regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
						  regval);
		  val += reg_size;
		  len -= reg_size;
		  regval = extract_unsigned_integer (val, reg_size,
						     byte_order);
		}
	      regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
	    }
	  else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
	    {
	      /* there's room in a register */
	      reg_size = register_size (gdbarch, argreg);
	      regval = extract_unsigned_integer (val, reg_size, byte_order);
	      regcache_cooked_write_unsigned (regcache, argreg++, regval);
	    }
	  /* Store the value one register at a time or in one step on
	     stack.  */
	  len -= reg_size;
	  val += reg_size;
	}
    }

  if (struct_return)
    {
      if (sh_is_renesas_calling_convention (func_type))
	/* If the function uses the Renesas ABI, subtract another 4 bytes from
	   the stack and store the struct return address there.  */
	write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
      else
	/* Using the gcc ABI, the "struct return pointer" pseudo-argument has
	   its own dedicated register.  */
	regcache_cooked_write_unsigned (regcache,
					STRUCT_RETURN_REGNUM, struct_addr);
    }

  /* Store return address.  */
  regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);

  /* Update stack pointer.  */
  regcache_cooked_write_unsigned (regcache,
				  gdbarch_sp_regnum (gdbarch), sp);

  return sp;
}

static CORE_ADDR
sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
			  struct value *function,
			  struct regcache *regcache,
			  CORE_ADDR bp_addr,
			  int nargs, struct value **args,
			  CORE_ADDR sp, int struct_return,
			  CORE_ADDR struct_addr)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  int stack_offset = 0;
  int argreg = ARG0_REGNUM;
  int argnum;
  struct type *func_type = value_type (function);
  struct type *type;
  CORE_ADDR regval;
  const gdb_byte *val;
  int len, reg_size = 0;
  int pass_on_stack = 0;
  int last_reg_arg = INT_MAX;

  /* The Renesas ABI expects all varargs arguments, plus the last
     non-vararg argument to be on the stack, no matter how many
     registers have been used so far.  */
  if (sh_is_renesas_calling_convention (func_type)
      && TYPE_VARARGS (func_type))
    last_reg_arg = TYPE_NFIELDS (func_type) - 2;

  /* First force sp to a 4-byte alignment.  */
  sp = sh_frame_align (gdbarch, sp);

  /* Make room on stack for args.  */
  sp -= sh_stack_allocsize (nargs, args);

  /* Now load as many as possible of the first arguments into
     registers, and push the rest onto the stack.  There are 16 bytes
     in four registers available.  Loop thru args from first to last.  */
  for (argnum = 0; argnum < nargs; argnum++)
    {
      type = value_type (args[argnum]);
      len = TYPE_LENGTH (type);
      val = sh_justify_value_in_reg (gdbarch, args[argnum], len);

      /* Some decisions have to be made how various types are handled.
	 This also differs in different ABIs.  */
      pass_on_stack = 0;
      /* Renesas ABI pushes doubles and long longs entirely on stack.
	 Same goes for aggregate types.  */
      if (sh_is_renesas_calling_convention (func_type)
	  && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
	      || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
	      || TYPE_CODE (type) == TYPE_CODE_STRUCT
	      || TYPE_CODE (type) == TYPE_CODE_UNION))
	pass_on_stack = 1;
      while (len > 0)
	{
	  if (argreg > ARGLAST_REGNUM || pass_on_stack
	      || argnum > last_reg_arg)
	    {
	      /* The remainder of the data goes entirely on the stack,
	         4-byte aligned.  */
	      reg_size = (len + 3) & ~3;
	      write_memory (sp + stack_offset, val, reg_size);
	      stack_offset += reg_size;
	    }
	  else if (argreg <= ARGLAST_REGNUM)
	    {
	      /* There's room in a register.  */
	      reg_size = register_size (gdbarch, argreg);
	      regval = extract_unsigned_integer (val, reg_size, byte_order);
	      regcache_cooked_write_unsigned (regcache, argreg++, regval);
	    }
	  /* Store the value reg_size bytes at a time.  This means that things
	     larger than reg_size bytes may go partly in registers and partly
	     on the stack.  */
	  len -= reg_size;
	  val += reg_size;
	}
    }

  if (struct_return)
    {
      if (sh_is_renesas_calling_convention (func_type))
	/* If the function uses the Renesas ABI, subtract another 4 bytes from
	   the stack and store the struct return address there.  */
	write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
      else
	/* Using the gcc ABI, the "struct return pointer" pseudo-argument has
	   its own dedicated register.  */
	regcache_cooked_write_unsigned (regcache,
					STRUCT_RETURN_REGNUM, struct_addr);
    }

  /* Store return address.  */
  regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);

  /* Update stack pointer.  */
  regcache_cooked_write_unsigned (regcache,
				  gdbarch_sp_regnum (gdbarch), sp);

  return sp;
}

/* Find a function's return value in the appropriate registers (in
   regbuf), and copy it into valbuf.  Extract from an array REGBUF
   containing the (raw) register state a function return value of type
   TYPE, and copy that, in virtual format, into VALBUF.  */
static void
sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
			       gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = regcache->arch ();
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  int len = TYPE_LENGTH (type);

  if (len <= 4)
    {
      ULONGEST c;

      regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
      store_unsigned_integer (valbuf, len, byte_order, c);
    }
  else if (len == 8)
    {
      int i, regnum = R0_REGNUM;
      for (i = 0; i < len; i += 4)
	regcache_raw_read (regcache, regnum++, valbuf + i);
    }
  else
    error (_("bad size for return value"));
}

static void
sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
			     gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = regcache->arch ();
  if (sh_treat_as_flt_p (type))
    {
      int len = TYPE_LENGTH (type);
      int i, regnum = gdbarch_fp0_regnum (gdbarch);
      for (i = 0; i < len; i += 4)
	if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
	  regcache_raw_read (regcache, regnum++,
			     valbuf + len - 4 - i);
	else
	  regcache_raw_read (regcache, regnum++, valbuf + i);
    }
  else
    sh_extract_return_value_nofpu (type, regcache, valbuf);
}

/* Write into appropriate registers a function return value
   of type TYPE, given in virtual format.
   If the architecture is sh4 or sh3e, store a function's return value
   in the R0 general register or in the FP0 floating point register,
   depending on the type of the return value.  In all the other cases
   the result is stored in r0, left-justified.  */
static void
sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
			     const gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = regcache->arch ();
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  ULONGEST val;
  int len = TYPE_LENGTH (type);

  if (len <= 4)
    {
      val = extract_unsigned_integer (valbuf, len, byte_order);
      regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
    }
  else
    {
      int i, regnum = R0_REGNUM;
      for (i = 0; i < len; i += 4)
	regcache_raw_write (regcache, regnum++, valbuf + i);
    }
}

static void
sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
			   const gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = regcache->arch ();
  if (sh_treat_as_flt_p (type))
    {
      int len = TYPE_LENGTH (type);
      int i, regnum = gdbarch_fp0_regnum (gdbarch);
      for (i = 0; i < len; i += 4)
	if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
	  regcache_raw_write (regcache, regnum++,
			      valbuf + len - 4 - i);
	else
	  regcache_raw_write (regcache, regnum++, valbuf + i);
    }
  else
    sh_store_return_value_nofpu (type, regcache, valbuf);
}

static enum return_value_convention
sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function,
		       struct type *type, struct regcache *regcache,
		       gdb_byte *readbuf, const gdb_byte *writebuf)
{
  struct type *func_type = function ? value_type (function) : NULL;

  if (sh_use_struct_convention_nofpu (
  	sh_is_renesas_calling_convention (func_type), type))
    return RETURN_VALUE_STRUCT_CONVENTION;
  if (writebuf)
    sh_store_return_value_nofpu (type, regcache, writebuf);
  else if (readbuf)
    sh_extract_return_value_nofpu (type, regcache, readbuf);
  return RETURN_VALUE_REGISTER_CONVENTION;
}

static enum return_value_convention
sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function,
		     struct type *type, struct regcache *regcache,
		     gdb_byte *readbuf, const gdb_byte *writebuf)
{
  struct type *func_type = function ? value_type (function) : NULL;

  if (sh_use_struct_convention (
	sh_is_renesas_calling_convention (func_type), type))
    return RETURN_VALUE_STRUCT_CONVENTION;
  if (writebuf)
    sh_store_return_value_fpu (type, regcache, writebuf);
  else if (readbuf)
    sh_extract_return_value_fpu (type, regcache, readbuf);
  return RETURN_VALUE_REGISTER_CONVENTION;
}

static struct type *
sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
{
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
    return builtin_type (gdbarch)->builtin_float;
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
    return builtin_type (gdbarch)->builtin_double;
  else
    return builtin_type (gdbarch)->builtin_int;
}

/* Return the GDB type object for the "standard" data type
   of data in register N.  */
static struct type *
sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
{
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
    return builtin_type (gdbarch)->builtin_float;
  else
    return builtin_type (gdbarch)->builtin_int;
}

static struct type *
sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
{
  return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
				  0, high);
}

static struct type *
sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
{
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
    return builtin_type (gdbarch)->builtin_float;
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
    return builtin_type (gdbarch)->builtin_double;
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
    return sh_sh4_build_float_register_type (gdbarch, 3);
  else
    return builtin_type (gdbarch)->builtin_int;
}

static struct type *
sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
{
  return builtin_type (gdbarch)->builtin_int;
}

/* Is a register in a reggroup?
   The default code in reggroup.c doesn't identify system registers, some
   float registers or any of the vector registers.
   TODO: sh2a and dsp registers.  */
static int
sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
			struct reggroup *reggroup)
{
  if (gdbarch_register_name (gdbarch, regnum) == NULL
      || *gdbarch_register_name (gdbarch, regnum) == '\0')
    return 0;

  if (reggroup == float_reggroup
      && (regnum == FPUL_REGNUM
	  || regnum == FPSCR_REGNUM))
    return 1;

  if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
    {
      if (reggroup == vector_reggroup || reggroup == float_reggroup)
	return 1;
      if (reggroup == general_reggroup)
	return 0;
    }

  if (regnum == VBR_REGNUM
      || regnum == SR_REGNUM
      || regnum == FPSCR_REGNUM
      || regnum == SSR_REGNUM
      || regnum == SPC_REGNUM)
    {
      if (reggroup == system_reggroup)
	return 1;
      if (reggroup == general_reggroup)
	return 0;
    }

  /* The default code can cope with any other registers.  */
  return default_register_reggroup_p (gdbarch, regnum, reggroup);
}

/* On the sh4, the DRi pseudo registers are problematic if the target
   is little endian.  When the user writes one of those registers, for
   instance with 'set var $dr0=1', we want the double to be stored
   like this: 
   fr0 = 0x00 0x00 0xf0 0x3f 
   fr1 = 0x00 0x00 0x00 0x00 

   This corresponds to little endian byte order & big endian word
   order.  However if we let gdb write the register w/o conversion, it
   will write fr0 and fr1 this way:
   fr0 = 0x00 0x00 0x00 0x00
   fr1 = 0x00 0x00 0xf0 0x3f
   because it will consider fr0 and fr1 as a single LE stretch of memory.
   
   To achieve what we want we must force gdb to store things in
   floatformat_ieee_double_littlebyte_bigword (which is defined in
   include/floatformat.h and libiberty/floatformat.c.

   In case the target is big endian, there is no problem, the
   raw bytes will look like:
   fr0 = 0x3f 0xf0 0x00 0x00
   fr1 = 0x00 0x00 0x00 0x00

   The other pseudo registers (the FVs) also don't pose a problem
   because they are stored as 4 individual FP elements.  */

static struct type *
sh_littlebyte_bigword_type (struct gdbarch *gdbarch)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  if (tdep->sh_littlebyte_bigword_type == NULL)
    tdep->sh_littlebyte_bigword_type
      = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword",
                         floatformats_ieee_double_littlebyte_bigword);

  return tdep->sh_littlebyte_bigword_type;
}

static void
sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
				struct type *type, gdb_byte *from, gdb_byte *to)
{
  if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
    {
      /* It is a no-op.  */
      memcpy (to, from, register_size (gdbarch, regnum));
      return;
    }

  if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
    target_float_convert (from, sh_littlebyte_bigword_type (gdbarch),
			  to, type);
  else
    error
      ("sh_register_convert_to_virtual called with non DR register number");
}

static void
sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
			    int regnum, const gdb_byte *from, gdb_byte *to)
{
  if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
    {
      /* It is a no-op.  */
      memcpy (to, from, register_size (gdbarch, regnum));
      return;
    }

  if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
    target_float_convert (from, type,
			  to, sh_littlebyte_bigword_type (gdbarch));
  else
    error (_("sh_register_convert_to_raw called with non DR register number"));
}

/* For vectors of 4 floating point registers.  */
static int
fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
{
  int fp_regnum;

  fp_regnum = gdbarch_fp0_regnum (gdbarch)
	      + (fv_regnum - FV0_REGNUM) * 4;
  return fp_regnum;
}

/* For double precision floating point registers, i.e 2 fp regs.  */
static int
dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
{
  int fp_regnum;

  fp_regnum = gdbarch_fp0_regnum (gdbarch)
	      + (dr_regnum - DR0_REGNUM) * 2;
  return fp_regnum;
}

/* Concatenate PORTIONS contiguous raw registers starting at
   BASE_REGNUM into BUFFER.  */

static enum register_status
pseudo_register_read_portions (struct gdbarch *gdbarch,
			       struct regcache *regcache,
			       int portions,
			       int base_regnum, gdb_byte *buffer)
{
  int portion;

  for (portion = 0; portion < portions; portion++)
    {
      enum register_status status;
      gdb_byte *b;

      b = buffer + register_size (gdbarch, base_regnum) * portion;
      status = regcache_raw_read (regcache, base_regnum + portion, b);
      if (status != REG_VALID)
	return status;
    }

  return REG_VALID;
}

static enum register_status
sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
			 int reg_nr, gdb_byte *buffer)
{
  int base_regnum;
  enum register_status status;

  if (reg_nr == PSEUDO_BANK_REGNUM)
    return regcache_raw_read (regcache, BANK_REGNUM, buffer);
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
    {
      /* Enough space for two float registers.  */
      gdb_byte temp_buffer[4 * 2];
      base_regnum = dr_reg_base_num (gdbarch, reg_nr);

      /* Build the value in the provided buffer.  */
      /* Read the real regs for which this one is an alias.  */
      status = pseudo_register_read_portions (gdbarch, regcache,
					      2, base_regnum, temp_buffer);
      if (status == REG_VALID)
	{
	  /* We must pay attention to the endiannes. */
	  sh_register_convert_to_virtual (gdbarch, reg_nr,
					  register_type (gdbarch, reg_nr),
					  temp_buffer, buffer);
	}
      return status;
    }
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
    {
      base_regnum = fv_reg_base_num (gdbarch, reg_nr);

      /* Read the real regs for which this one is an alias.  */
      return pseudo_register_read_portions (gdbarch, regcache,
					    4, base_regnum, buffer);
    }
  else
    gdb_assert_not_reached ("invalid pseudo register number");
}

static void
sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
			  int reg_nr, const gdb_byte *buffer)
{
  int base_regnum, portion;

  if (reg_nr == PSEUDO_BANK_REGNUM)
    {
      /* When the bank register is written to, the whole register bank
         is switched and all values in the bank registers must be read
	 from the target/sim again.  We're just invalidating the regcache
	 so that a re-read happens next time it's necessary.  */
      int bregnum;

      regcache_raw_write (regcache, BANK_REGNUM, buffer);
      for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
        regcache_invalidate (regcache, bregnum);
    }
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
    {
      /* Enough space for two float registers.  */
      gdb_byte temp_buffer[4 * 2];
      base_regnum = dr_reg_base_num (gdbarch, reg_nr);

      /* We must pay attention to the endiannes.  */
      sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
				  reg_nr, buffer, temp_buffer);

      /* Write the real regs for which this one is an alias.  */
      for (portion = 0; portion < 2; portion++)
	regcache_raw_write (regcache, base_regnum + portion,
			    (temp_buffer
			     + register_size (gdbarch,
					      base_regnum) * portion));
    }
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
    {
      base_regnum = fv_reg_base_num (gdbarch, reg_nr);

      /* Write the real regs for which this one is an alias.  */
      for (portion = 0; portion < 4; portion++)
	regcache_raw_write (regcache, base_regnum + portion,
			    (buffer
			     + register_size (gdbarch,
					      base_regnum) * portion));
    }
}

static int
sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
{
  if (legacy_register_sim_regno (gdbarch, nr) < 0)
    return legacy_register_sim_regno (gdbarch, nr);
  if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
    return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
  if (nr == MOD_REGNUM)
    return SIM_SH_MOD_REGNUM;
  if (nr == RS_REGNUM)
    return SIM_SH_RS_REGNUM;
  if (nr == RE_REGNUM)
    return SIM_SH_RE_REGNUM;
  if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
    return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
  return nr;
}

static int
sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
{
  switch (nr)
    {
      case TBR_REGNUM:
        return SIM_SH_TBR_REGNUM;
      case IBNR_REGNUM:
        return SIM_SH_IBNR_REGNUM;
      case IBCR_REGNUM:
        return SIM_SH_IBCR_REGNUM;
      case BANK_REGNUM:
        return SIM_SH_BANK_REGNUM;
      case MACLB_REGNUM:
        return SIM_SH_BANK_MACL_REGNUM;
      case GBRB_REGNUM:
        return SIM_SH_BANK_GBR_REGNUM;
      case PRB_REGNUM:
        return SIM_SH_BANK_PR_REGNUM;
      case IVNB_REGNUM:
        return SIM_SH_BANK_IVN_REGNUM;
      case MACHB_REGNUM:
        return SIM_SH_BANK_MACH_REGNUM;
      default:
        break;
    }
  return legacy_register_sim_regno (gdbarch, nr);
}

/* Set up the register unwinding such that call-clobbered registers are
   not displayed in frames >0 because the true value is not certain.
   The 'undefined' registers will show up as 'not available' unless the
   CFI says otherwise.

   This function is currently set up for SH4 and compatible only.  */

static void
sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
                          struct dwarf2_frame_state_reg *reg,
			  struct frame_info *this_frame)
{
  /* Mark the PC as the destination for the return address.  */
  if (regnum == gdbarch_pc_regnum (gdbarch))
    reg->how = DWARF2_FRAME_REG_RA;

  /* Mark the stack pointer as the call frame address.  */
  else if (regnum == gdbarch_sp_regnum (gdbarch))
    reg->how = DWARF2_FRAME_REG_CFA;

  /* The above was taken from the default init_reg in dwarf2-frame.c
     while the below is SH specific.  */

  /* Caller save registers.  */
  else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
	   || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
	   || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
	   || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
	   || (regnum == MACH_REGNUM)
	   || (regnum == MACL_REGNUM)
	   || (regnum == FPUL_REGNUM)
	   || (regnum == SR_REGNUM))
    reg->how = DWARF2_FRAME_REG_UNDEFINED;

  /* Callee save registers.  */
  else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
	   || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
	   || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
	   || (regnum == FV0_REGNUM+3))
    reg->how = DWARF2_FRAME_REG_SAME_VALUE;

  /* Other registers.  These are not in the ABI and may or may not
     mean anything in frames >0 so don't show them.  */
  else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
	   || (regnum == GBR_REGNUM)
	   || (regnum == VBR_REGNUM)
	   || (regnum == FPSCR_REGNUM)
	   || (regnum == SSR_REGNUM)
	   || (regnum == SPC_REGNUM))
    reg->how = DWARF2_FRAME_REG_UNDEFINED;
}

static struct sh_frame_cache *
sh_alloc_frame_cache (void)
{
  struct sh_frame_cache *cache;
  int i;

  cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);

  /* Base address.  */
  cache->base = 0;
  cache->saved_sp = 0;
  cache->sp_offset = 0;
  cache->pc = 0;

  /* Frameless until proven otherwise.  */
  cache->uses_fp = 0;

  /* Saved registers.  We initialize these to -1 since zero is a valid
     offset (that's where fp is supposed to be stored).  */
  for (i = 0; i < SH_NUM_REGS; i++)
    {
      cache->saved_regs[i] = -1;
    }

  return cache;
}

static struct sh_frame_cache *
sh_frame_cache (struct frame_info *this_frame, void **this_cache)
{
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
  struct sh_frame_cache *cache;
  CORE_ADDR current_pc;
  int i;

  if (*this_cache)
    return (struct sh_frame_cache *) *this_cache;

  cache = sh_alloc_frame_cache ();
  *this_cache = cache;

  /* In principle, for normal frames, fp holds the frame pointer,
     which holds the base address for the current stack frame.
     However, for functions that don't need it, the frame pointer is
     optional.  For these "frameless" functions the frame pointer is
     actually the frame pointer of the calling frame.  */
  cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
  if (cache->base == 0)
    return cache;

  cache->pc = get_frame_func (this_frame);
  current_pc = get_frame_pc (this_frame);
  if (cache->pc != 0)
    {
      ULONGEST fpscr;

      /* Check for the existence of the FPSCR register.	 If it exists,
	 fetch its value for use in prologue analysis.	Passing a zero
	 value is the best choice for architecture variants upon which
	 there's no FPSCR register.  */
      if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup))
	fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
      else
	fpscr = 0;

      sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
    }

  if (!cache->uses_fp)
    {
      /* We didn't find a valid frame, which means that CACHE->base
         currently holds the frame pointer for our calling frame.  If
         we're at the start of a function, or somewhere half-way its
         prologue, the function's frame probably hasn't been fully
         setup yet.  Try to reconstruct the base address for the stack
         frame by looking at the stack pointer.  For truly "frameless"
         functions this might work too.  */
      cache->base = get_frame_register_unsigned
		     (this_frame, gdbarch_sp_regnum (gdbarch));
    }

  /* Now that we have the base address for the stack frame we can
     calculate the value of sp in the calling frame.  */
  cache->saved_sp = cache->base + cache->sp_offset;

  /* Adjust all the saved registers such that they contain addresses
     instead of offsets.  */
  for (i = 0; i < SH_NUM_REGS; i++)
    if (cache->saved_regs[i] != -1)
      cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;

  return cache;
}

static struct value *
sh_frame_prev_register (struct frame_info *this_frame,
			void **this_cache, int regnum)
{
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  gdb_assert (regnum >= 0);

  if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
    return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);

  /* The PC of the previous frame is stored in the PR register of
     the current frame.  Frob regnum so that we pull the value from
     the correct place.  */
  if (regnum == gdbarch_pc_regnum (gdbarch))
    regnum = PR_REGNUM;

  if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
    return frame_unwind_got_memory (this_frame, regnum,
                                    cache->saved_regs[regnum]);

  return frame_unwind_got_register (this_frame, regnum, regnum);
}

static void
sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
		  struct frame_id *this_id)
{
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  /* This marks the outermost frame.  */
  if (cache->base == 0)
    return;

  *this_id = frame_id_build (cache->saved_sp, cache->pc);
}

static const struct frame_unwind sh_frame_unwind = {
  NORMAL_FRAME,
  default_frame_unwind_stop_reason,
  sh_frame_this_id,
  sh_frame_prev_register,
  NULL,
  default_frame_sniffer
};

static CORE_ADDR
sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
  return frame_unwind_register_unsigned (next_frame,
					 gdbarch_sp_regnum (gdbarch));
}

static CORE_ADDR
sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
  return frame_unwind_register_unsigned (next_frame,
					 gdbarch_pc_regnum (gdbarch));
}

static struct frame_id
sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
{
  CORE_ADDR sp = get_frame_register_unsigned (this_frame,
					      gdbarch_sp_regnum (gdbarch));
  return frame_id_build (sp, get_frame_pc (this_frame));
}

static CORE_ADDR
sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
{
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  return cache->base;
}

static const struct frame_base sh_frame_base = {
  &sh_frame_unwind,
  sh_frame_base_address,
  sh_frame_base_address,
  sh_frame_base_address
};

static struct sh_frame_cache *
sh_make_stub_cache (struct frame_info *this_frame)
{
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
  struct sh_frame_cache *cache;

  cache = sh_alloc_frame_cache ();

  cache->saved_sp
    = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));

  return cache;
}

static void
sh_stub_this_id (struct frame_info *this_frame, void **this_cache,
                 struct frame_id *this_id)
{
  struct sh_frame_cache *cache;

  if (*this_cache == NULL)
    *this_cache = sh_make_stub_cache (this_frame);
  cache = (struct sh_frame_cache *) *this_cache;

  *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame));
}

static int
sh_stub_unwind_sniffer (const struct frame_unwind *self,
                        struct frame_info *this_frame,
                        void **this_prologue_cache)
{
  CORE_ADDR addr_in_block;

  addr_in_block = get_frame_address_in_block (this_frame);
  if (in_plt_section (addr_in_block))
    return 1;

  return 0;
}

static const struct frame_unwind sh_stub_unwind =
{
  NORMAL_FRAME,
  default_frame_unwind_stop_reason,
  sh_stub_this_id,
  sh_frame_prev_register,
  NULL,
  sh_stub_unwind_sniffer
};

/* Implement the stack_frame_destroyed_p gdbarch method.

   The epilogue is defined here as the area at the end of a function,
   either on the `ret' instruction itself or after an instruction which
   destroys the function's stack frame.  */

static int
sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  CORE_ADDR func_addr = 0, func_end = 0;

  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
    {
      ULONGEST inst;
      /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
         for a nop and some fixed data (e.g. big offsets) which are
         unfortunately also treated as part of the function (which
         means, they are below func_end.  */
      CORE_ADDR addr = func_end - 28;
      if (addr < func_addr + 4)
	addr = func_addr + 4;
      if (pc < addr)
	return 0;

      /* First search forward until hitting an rts.  */
      while (addr < func_end
	     && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
	addr += 2;
      if (addr >= func_end)
	return 0;

      /* At this point we should find a mov.l @r15+,r14 instruction,
         either before or after the rts.  If not, then the function has
         probably no "normal" epilogue and we bail out here.  */
      inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
      if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
						       byte_order)))
	addr -= 2;
      else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
							     byte_order)))
	return 0;

      inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);

      /* Step over possible lds.l @r15+,macl.  */
      if (IS_MACL_LDS (inst))
	{
	  addr -= 2;
	  inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
	}

      /* Step over possible lds.l @r15+,pr.  */
      if (IS_LDS (inst))
	{
	  addr -= 2;
	  inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
	}

      /* Step over possible mov r14,r15.  */
      if (IS_MOV_FP_SP (inst))
	{
	  addr -= 2;
	  inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
	}

      /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
         instructions.  */
      while (addr > func_addr + 4
	     && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
	{
	  addr -= 2;
	  inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
	}

      /* On SH2a check if the previous instruction was perhaps a MOVI20.
         That's allowed for the epilogue.  */
      if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
           || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
          && addr > func_addr + 6
	  && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
						      byte_order)))
	addr -= 4;

      if (pc >= addr)
	return 1;
    }
  return 0;
}


/* Supply register REGNUM from the buffer specified by REGS and LEN
   in the register set REGSET to register cache REGCACHE.
   REGTABLE specifies where each register can be found in REGS.
   If REGNUM is -1, do this for all registers in REGSET.  */

void
sh_corefile_supply_regset (const struct regset *regset,
			   struct regcache *regcache,
			   int regnum, const void *regs, size_t len)
{
  struct gdbarch *gdbarch = regcache->arch ();
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
					     ? tdep->core_gregmap
					     : tdep->core_fpregmap);
  int i;

  for (i = 0; regmap[i].regnum != -1; i++)
    {
      if ((regnum == -1 || regnum == regmap[i].regnum)
	  && regmap[i].offset + 4 <= len)
	regcache_raw_supply (regcache, regmap[i].regnum,
			     (char *)regs + regmap[i].offset);
    }
}

/* Collect register REGNUM in the register set REGSET from register cache
   REGCACHE into the buffer specified by REGS and LEN.
   REGTABLE specifies where each register can be found in REGS.
   If REGNUM is -1, do this for all registers in REGSET.  */

void
sh_corefile_collect_regset (const struct regset *regset,
			    const struct regcache *regcache,
			    int regnum, void *regs, size_t len)
{
  struct gdbarch *gdbarch = regcache->arch ();
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
					     ? tdep->core_gregmap
					     : tdep->core_fpregmap);
  int i;

  for (i = 0; regmap[i].regnum != -1; i++)
    {
      if ((regnum == -1 || regnum == regmap[i].regnum)
	  && regmap[i].offset + 4 <= len)
	regcache_raw_collect (regcache, regmap[i].regnum,
			      (char *)regs + regmap[i].offset);
    }
}

/* The following two regsets have the same contents, so it is tempting to
   unify them, but they are distiguished by their address, so don't.  */

const struct regset sh_corefile_gregset =
{
  NULL,
  sh_corefile_supply_regset,
  sh_corefile_collect_regset
};

static const struct regset sh_corefile_fpregset =
{
  NULL,
  sh_corefile_supply_regset,
  sh_corefile_collect_regset
};

static void
sh_iterate_over_regset_sections (struct gdbarch *gdbarch,
				 iterate_over_regset_sections_cb *cb,
				 void *cb_data,
				 const struct regcache *regcache)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  if (tdep->core_gregmap != NULL)
    cb (".reg", tdep->sizeof_gregset, &sh_corefile_gregset, NULL, cb_data);

  if (tdep->core_fpregmap != NULL)
    cb (".reg2", tdep->sizeof_fpregset, &sh_corefile_fpregset, NULL, cb_data);
}

/* This is the implementation of gdbarch method
   return_in_first_hidden_param_p.  */

static int
sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
				     struct type *type)
{
  return 0;
}



static struct gdbarch *
sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
  struct gdbarch *gdbarch;
  struct gdbarch_tdep *tdep;

  /* SH5 is handled entirely in sh64-tdep.c.  */
  if (info.bfd_arch_info->mach == bfd_mach_sh5)
    return sh64_gdbarch_init (info, arches);

  /* If there is already a candidate, use it.  */
  arches = gdbarch_list_lookup_by_info (arches, &info);
  if (arches != NULL)
    return arches->gdbarch;

  /* None found, create a new architecture from the information
     provided.  */
  tdep = XCNEW (struct gdbarch_tdep);
  gdbarch = gdbarch_alloc (&info, tdep);

  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);

  set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT);
  set_gdbarch_wchar_signed (gdbarch, 0);

  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
  set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
  set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);

  set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
  set_gdbarch_sp_regnum (gdbarch, 15);
  set_gdbarch_pc_regnum (gdbarch, 16);
  set_gdbarch_fp0_regnum (gdbarch, -1);
  set_gdbarch_num_pseudo_regs (gdbarch, 0);

  set_gdbarch_register_type (gdbarch, sh_default_register_type);
  set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);

  set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc);
  set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind);

  set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);

  set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);

  set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);

  set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
  set_gdbarch_return_in_first_hidden_param_p (gdbarch,
					      sh_return_in_first_hidden_param_p);

  set_gdbarch_believe_pcc_promotion (gdbarch, 1);

  set_gdbarch_frame_align (gdbarch, sh_frame_align);
  set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
  set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
  set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
  frame_base_set_default (gdbarch, &sh_frame_base);

  set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p);

  dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);

  set_gdbarch_iterate_over_regset_sections
    (gdbarch, sh_iterate_over_regset_sections);

  switch (info.bfd_arch_info->mach)
    {
    case bfd_mach_sh:
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
      break;

    case bfd_mach_sh2:
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
      break;

    case bfd_mach_sh2e:
      /* doubles on sh2e and sh3e are actually 4 byte.  */
      set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
      set_gdbarch_double_format (gdbarch, floatformats_ieee_single);

      set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
      set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
      set_gdbarch_fp0_regnum (gdbarch, 25);
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
      break;

    case bfd_mach_sh2a:
      set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
      set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
      set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);

      set_gdbarch_fp0_regnum (gdbarch, 25);
      set_gdbarch_num_pseudo_regs (gdbarch, 9);
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
      break;

    case bfd_mach_sh2a_nofpu:
      set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
      set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);

      set_gdbarch_num_pseudo_regs (gdbarch, 1);
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
      break;

    case bfd_mach_sh_dsp:
      set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
      break;

    case bfd_mach_sh3:
    case bfd_mach_sh3_nommu:
    case bfd_mach_sh2a_nofpu_or_sh3_nommu:
      set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
      break;

    case bfd_mach_sh3e:
    case bfd_mach_sh2a_or_sh3e:
      /* doubles on sh2e and sh3e are actually 4 byte.  */
      set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
      set_gdbarch_double_format (gdbarch, floatformats_ieee_single);

      set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
      set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
      set_gdbarch_fp0_regnum (gdbarch, 25);
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
      break;

    case bfd_mach_sh3_dsp:
      set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
      break;

    case bfd_mach_sh4:
    case bfd_mach_sh4a:
    case bfd_mach_sh2a_or_sh4:
      set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
      set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
      set_gdbarch_fp0_regnum (gdbarch, 25);
      set_gdbarch_num_pseudo_regs (gdbarch, 13);
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
      break;

    case bfd_mach_sh4_nofpu:
    case bfd_mach_sh4a_nofpu:
    case bfd_mach_sh4_nommu_nofpu:
    case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
      set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
      break;

    case bfd_mach_sh4al_dsp:
      set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
      break;

    default:
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
      break;
    }

  /* Hook in ABI-specific overrides, if they have been registered.  */
  gdbarch_init_osabi (info, gdbarch);

  dwarf2_append_unwinders (gdbarch);
  frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind);
  frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);

  return gdbarch;
}

static void
show_sh_command (const char *args, int from_tty)
{
  help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
}

static void
set_sh_command (const char *args, int from_tty)
{
  printf_unfiltered
    ("\"set sh\" must be followed by an appropriate subcommand.\n");
  help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
}

void
_initialize_sh_tdep (void)
{
  gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);

  add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
                  &setshcmdlist, "set sh ", 0, &setlist);
  add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
                  &showshcmdlist, "show sh ", 0, &showlist);
  
  add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
			&sh_active_calling_convention,
			_("Set calling convention used when calling target "
			  "functions from GDB."),
			_("Show calling convention used when calling target "
			  "functions from GDB."),
			_("gcc       - Use GCC calling convention (default).\n"
			  "renesas   - Enforce Renesas calling convention."),
			NULL, NULL,
			&setshcmdlist, &showshcmdlist);
}