1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
|
@c Copyright (C) 2001-2023 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
@ifset GENERIC
@page
@node PPC-Dependent
@chapter PowerPC Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter PowerPC Dependent Features
@end ifclear
@cindex PowerPC support
@menu
* PowerPC-Opts:: Options
* PowerPC-Pseudo:: PowerPC Assembler Directives
* PowerPC-Syntax:: PowerPC Syntax
@end menu
@node PowerPC-Opts
@section Options
@cindex options for PowerPC
@cindex PowerPC options
@cindex architectures, PowerPC
@cindex PowerPC architectures
The PowerPC chip family includes several successive levels, using the same
core instruction set, but including a few additional instructions at
each level. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
The following table lists all available PowerPC options.
@c man begin OPTIONS
@table @gcctabopt
@item -a32
Generate ELF32 or XCOFF32.
@item -a64
Generate ELF64 or XCOFF64.
@item -K PIC
Set EF_PPC_RELOCATABLE_LIB in ELF flags.
@item -mpwrx | -mpwr2
Generate code for POWER/2 (RIOS2).
@item -mpwr
Generate code for POWER (RIOS1)
@item -m601
Generate code for PowerPC 601.
@item -mppc, -mppc32, -m603, -m604
Generate code for PowerPC 603/604.
@item -m403, -m405
Generate code for PowerPC 403/405.
@item -m440
Generate code for PowerPC 440. BookE and some 405 instructions.
@item -m464
Generate code for PowerPC 464.
@item -m476
Generate code for PowerPC 476.
@item -m7400, -m7410, -m7450, -m7455
Generate code for PowerPC 7400/7410/7450/7455.
@item -m750cl, -mgekko, -mbroadway
Generate code for PowerPC 750CL/Gekko/Broadway.
@item -m821, -m850, -m860
Generate code for PowerPC 821/850/860.
@item -mppc64, -m620
Generate code for PowerPC 620/625/630.
@item -me200z2, -me200z4
Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
@item -me300
Generate code for PowerPC e300 family.
@item -me500, -me500x2
Generate code for Motorola e500 core complex.
@item -me500mc
Generate code for Freescale e500mc core complex.
@item -me500mc64
Generate code for Freescale e500mc64 core complex.
@item -me5500
Generate code for Freescale e5500 core complex.
@item -me6500
Generate code for Freescale e6500 core complex.
@item -mlsp
Enable LSP instructions. (Disables SPE and SPE2.)
@item -mspe
Generate code for Motorola SPE instructions. (Disables LSP.)
@item -mspe2
Generate code for Freescale SPE2 instructions. (Disables LSP.)
@item -mtitan
Generate code for AppliedMicro Titan core complex.
@item -mppc64bridge
Generate code for PowerPC 64, including bridge insns.
@item -mbooke
Generate code for 32-bit BookE.
@item -ma2
Generate code for A2 architecture.
@item -maltivec
Generate code for processors with AltiVec instructions.
@item -mvle
Generate code for Freescale PowerPC VLE instructions.
@item -mvsx
Generate code for processors with Vector-Scalar (VSX) instructions.
@item -mhtm
Generate code for processors with Hardware Transactional Memory instructions.
@item -mpower4, -mpwr4
Generate code for Power4 architecture.
@item -mpower5, -mpwr5, -mpwr5x
Generate code for Power5 architecture.
@item -mpower6, -mpwr6
Generate code for Power6 architecture.
@item -mpower7, -mpwr7
Generate code for Power7 architecture.
@item -mpower8, -mpwr8
Generate code for Power8 architecture.
@item -mpower9, -mpwr9
Generate code for Power9 architecture.
@item -mpower10, -mpwr10
Generate code for Power10 architecture.
@item -mfuture
Generate code for 'future' architecture.
@item -mcell
@item -mcell
Generate code for Cell Broadband Engine architecture.
@item -mcom
Generate code Power/PowerPC common instructions.
@item -many
Generate code for any architecture (PWR/PWRX/PPC).
@item -mregnames
Allow symbolic names for registers.
@item -mno-regnames
Do not allow symbolic names for registers.
@item -mrelocatable
Support for GCC's -mrelocatable option.
@item -mrelocatable-lib
Support for GCC's -mrelocatable-lib option.
@item -memb
Set PPC_EMB bit in ELF flags.
@item -mlittle, -mlittle-endian, -le
Generate code for a little endian machine.
@item -mbig, -mbig-endian, -be
Generate code for a big endian machine.
@item -msolaris
Generate code for Solaris.
@item -mno-solaris
Do not generate code for Solaris.
@item -nops=@var{count}
If an alignment directive inserts more than @var{count} nops, put a
branch at the beginning to skip execution of the nops.
@end table
@c man end
@node PowerPC-Pseudo
@section PowerPC Assembler Directives
@cindex directives for PowerPC
@cindex PowerPC directives
A number of assembler directives are available for PowerPC. The
following table is far from complete.
@table @code
@item .machine "string"
This directive allows you to change the machine for which code is
generated. @code{"string"} may be any of the -m cpu selection options
(without the -m) enclosed in double quotes, @code{"push"}, or
@code{"pop"}. @code{.machine "push"} saves the currently selected
cpu, which may be restored with @code{.machine "pop"}.
@end table
@node PowerPC-Syntax
@section PowerPC Syntax
@menu
* PowerPC-Chars:: Special Characters
@end menu
@node PowerPC-Chars
@subsection Special Characters
@cindex line comment character, PowerPC
@cindex PowerPC line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line.
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
If the assembler has been configured for the ppc-*-solaris* target
then the @samp{!} character also acts as a line comment character.
This can be disabled via the @option{-mno-solaris} command-line
option.
@cindex line separator, PowerPC
@cindex statement separator, PowerPC
@cindex PowerPC line separator
The @samp{;} character can be used to separate statements on the same
line.
|
