aboutsummaryrefslogtreecommitdiff
path: root/gas/doc/c-aarch64.texi
blob: 2c236e2c84a202598dcd16e70e4924e64575dcd8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
@c Copyright (C) 2009-2019 Free Software Foundation, Inc.
@c Contributed by ARM Ltd.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end

@ifset GENERIC
@page
@node AArch64-Dependent
@chapter AArch64 Dependent Features
@end ifset

@ifclear GENERIC
@node Machine Dependencies
@chapter AArch64 Dependent Features
@end ifclear

@cindex AArch64 support
@menu
* AArch64 Options::              Options
* AArch64 Extensions::		 Extensions
* AArch64 Syntax::               Syntax
* AArch64 Floating Point::       Floating Point
* AArch64 Directives::           AArch64 Machine Directives
* AArch64 Opcodes::              Opcodes
* AArch64 Mapping Symbols::      Mapping Symbols
@end menu

@node AArch64 Options
@section Options
@cindex AArch64 options (none)
@cindex options for AArch64 (none)

@c man begin OPTIONS
@table @gcctabopt

@cindex @option{-EB} command-line option, AArch64
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.

@cindex @option{-EL} command-line option, AArch64
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.

@cindex @option{-mabi=} command-line option, AArch64
@item -mabi=@var{abi}
Specify which ABI the source code uses.  The recognized arguments
are: @code{ilp32} and @code{lp64}, which decides the generated object
file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.

@cindex @option{-mcpu=} command-line option, AArch64
@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor.  The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor.  The following processor names are recognized:
@code{cortex-a34},
@code{cortex-a35},
@code{cortex-a53},
@code{cortex-a55},
@code{cortex-a57},
@code{cortex-a65},
@code{cortex-a65ae},
@code{cortex-a72},
@code{cortex-a73},
@code{cortex-a75},
@code{cortex-a76},
@code{cortex-a76ae},
@code{cortex-a77},
@code{ares},
@code{exynos-m1},
@code{falkor},
@code{neoverse-n1},
@code{neoverse-e1},
@code{qdf24xx},
@code{saphira},
@code{thunderx},
@code{vulcan},
@code{xgene1}
and
@code{xgene2}.
The special name @code{all} may be used to allow the assembler to accept
instructions valid for any supported processor, including all optional
extensions.

In addition to the basic instruction set, the assembler can be told to
accept, or restrict, various extension mnemonics that extend the
processor.  @xref{AArch64 Extensions}.

If some implementations of a particular processor can have an
extension, then then those extensions are automatically enabled.
Consequently, you will not normally have to specify any additional
extensions.

@cindex @option{-march=} command-line option, AArch64
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture.  The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture.  The
following architecture names are recognized: @code{armv8-a},
@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
and @code{armv8.5-a}.

If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}.  If neither are
specified, the assembler will default to @option{-mcpu=all}.

The architecture option can be extended with the same instruction set
extension options as the @option{-mcpu} option.  Unlike
@option{-mcpu}, extensions are not always enabled by default,
@xref{AArch64 Extensions}.

@cindex @code{-mverbose-error} command-line option, AArch64
@item -mverbose-error
This option enables verbose error messages for AArch64 gas.  This option
is enabled by default.

@cindex @code{-mno-verbose-error} command-line option, AArch64
@item -mno-verbose-error
This option disables verbose error messages in AArch64 gas.

@end table
@c man end

@node AArch64 Extensions
@section Architecture Extensions

The table below lists the permitted architecture extensions that are
supported by the assembler and the conditions under which they are
automatically enabled.

Multiple extensions may be specified, separated by a @code{+}.
Extension mnemonics may also be removed from those the assembler
accepts.  This is done by prepending @code{no} to the option that adds
the extension.  Extensions that are removed must be listed after all
extensions that have been added.

Enabling an extension that requires other extensions will
automatically cause those extensions to be enabled.  Similarly,
disabling an extension that is required by other extensions will
automatically cause those extensions to be disabled.

@multitable @columnfractions .12 .17 .17 .54
@headitem Extension @tab Minimum Architecture @tab Enabled by default
 @tab Description
@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 @tab Enable the complex number SIMD extensions.  This implies
 @code{fp16} and @code{simd}.
@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable CRC instructions.
@item @code{crypto} @tab ARMv8-A @tab No
 @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
@item @code{aes} @tab ARMv8-A @tab No
 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
@item @code{sha2} @tab ARMv8-A @tab No
 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
@item @code{sha3} @tab ARMv8.2-A @tab No
 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
@item @code{sm4} @tab ARMv8.2-A @tab No
 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 @tab Enable floating-point extensions.
@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 @code{fp}.
@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable Limited Ordering Regions extensions.
@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable Large System extensions.
@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable Privileged Access Never support.
@item @code{profile} @tab ARMv8.2-A @tab No
 @tab Enable statistical profiling extensions.
@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 @tab Enable the Reliability, Availability and Serviceability
 extension.
@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 @tab Enable the weak release consistency extension.
@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
@item @code{sve} @tab ARMv8.2-A @tab No
 @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 @code{simd} and @code{compnum}.
@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 @tab Enable the Dot Product extension.  This implies @code{simd}.
@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 This implies @code{fp16}.
@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 @tab Enable the speculation barrier instruction sb.
@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 @tab Enable the Execution and Data and Prediction instructions.
@item @code{rng} @tab ARMv8.5-A @tab No
 @tab Enable ARMv8.5-A random number instructions.
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 @tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{memtag} @tab ARMv8.5-A @tab No
 @tab Enable ARMv8.5-A Memory Tagging Extensions.
@item @code{tme} @tab ARMv8-A @tab No
 @tab Enable Transactional Memory Extensions.
@item @code{sve2} @tab ARMv8-A @tab No
 @tab Enable the SVE2 Extension.
@item @code{sve2-bitperm} @tab ARMv8-A @tab No
 @tab Enable SVE2 BITPERM Extension.
@item @code{sve2-sm4} @tab ARMv8-A @tab No
 @tab Enable SVE2 SM4 Extension.
@item @code{sve2-aes} @tab ARMv8-A @tab No
 @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 @code{pmullt} and @code{pmullb} instructions.
@item @code{sve2-sha3} @tab ARMv8-A @tab No
 @tab Enable SVE2 SHA3 Extension.
@end multitable

@node AArch64 Syntax
@section Syntax
@menu
* AArch64-Chars::                Special Characters
* AArch64-Regs::                 Register Names
* AArch64-Relocations::	     Relocations
@end menu

@node AArch64-Chars
@subsection Special Characters

@cindex line comment character, AArch64
@cindex AArch64 line comment character
The presence of a @samp{//} on a line indicates the start of a comment
that extends to the end of the current line.  If a @samp{#} appears as
the first character of a line, the whole line is treated as a comment.

@cindex line separator, AArch64
@cindex statement separator, AArch64
@cindex AArch64 line separator
The @samp{;} character can be used instead of a newline to separate
statements.

@cindex immediate character, AArch64
@cindex AArch64 immediate character
The @samp{#} can be optionally used to indicate immediate operands.

@node AArch64-Regs
@subsection Register Names

@cindex AArch64 register names
@cindex register names, AArch64
Please refer to the section @samp{4.4 Register Names} of
@samp{ARMv8 Instruction Set Overview}, which is available at
@uref{http://infocenter.arm.com}.

@node AArch64-Relocations
@subsection Relocations

@cindex relocations, AArch64
@cindex AArch64 relocations
@cindex MOVN, MOVZ and MOVK group relocations, AArch64
Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
by prefixing the label with @samp{#:abs_g2:} etc.
For example to load the 48-bit absolute address of @var{foo} into x0:

@smallexample
        movz x0, #:abs_g2:foo		// bits 32-47, overflow check
        movk x0, #:abs_g1_nc:foo	// bits 16-31, no overflow check
        movk x0, #:abs_g0_nc:foo	// bits  0-15, no overflow check
@end smallexample

@cindex ADRP, ADD, LDR/STR group relocations, AArch64
Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
instructions can be generated by prefixing the label with
@samp{:pg_hi21:} and @samp{#:lo12:} respectively.

For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:

@smallexample
        adrp x0, :pg_hi21:foo
        add  x0, x0, #:lo12:foo
@end smallexample

Or to load the value of @var{foo} into x0:

@smallexample
        adrp x0, :pg_hi21:foo
        ldr  x0, [x0, #:lo12:foo]
@end smallexample

Note that @samp{:pg_hi21:} is optional.

@smallexample
        adrp x0, foo
@end smallexample

is equivalent to

@smallexample
        adrp x0, :pg_hi21:foo
@end smallexample

@node AArch64 Floating Point
@section Floating Point

@cindex floating point, AArch64 (@sc{ieee})
@cindex AArch64 floating point (@sc{ieee})
The AArch64 architecture uses @sc{ieee} floating-point numbers.

@node AArch64 Directives
@section AArch64 Machine Directives

@cindex machine directives, AArch64
@cindex AArch64 machine directives
@table @code

@c AAAAAAAAAAAAAAAAAAAAAAAAA

@cindex @code{.arch} directive, AArch64
@item .arch @var{name}
Select the target architecture.  Valid values for @var{name} are the same as
for the @option{-march} command-line option.

Specifying @code{.arch} clears any previously selected architecture
extensions.

@cindex @code{.arch_extension} directive, AArch64
@item .arch_extension @var{name}
Add or remove an architecture extension to the target architecture.  Valid
values for @var{name} are the same as those accepted as architectural
extensions by the @option{-mcpu} command-line option.

@code{.arch_extension} may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.

@c BBBBBBBBBBBBBBBBBBBBBBBBBB

@cindex @code{.bss} directive, AArch64
@item .bss
This directive switches to the @code{.bss} section.

@c CCCCCCCCCCCCCCCCCCCCCCCCCC

@cindex @code{.cpu} directive, AArch64
@item .cpu @var{name}
Set the target processor.  Valid values for @var{name} are the same as
those accepted by the @option{-mcpu=} command-line option.

@c DDDDDDDDDDDDDDDDDDDDDDDDDD

@cindex @code{.dword} directive, AArch64
@item .dword @var{expressions}
The @code{.dword} directive produces 64 bit values.

@c EEEEEEEEEEEEEEEEEEEEEEEEEE

@cindex @code{.even} directive, AArch64
@item .even
The @code{.even} directive aligns the output on the next even byte
boundary.

@c FFFFFFFFFFFFFFFFFFFFFFFFFF

@cindex @code{.float16} directive, AArch64
@item .float16 @var{value [,...,value_n]}
Place the half precision floating point representation of one or more
floating-point values into the current section.
The format used to encode the floating point values is always the
IEEE 754-2008 half precision floating point format.

@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII

@cindex @code{.inst} directive, AArch64
@item .inst @var{expressions}
Inserts the expressions into the output as if they were instructions,
rather than data.

@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL

@cindex @code{.ltorg} directive, AArch64
@item .ltorg
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
GAS maintains a separate literal pool for each section and each
sub-section.  The @code{.ltorg} directive will only affect the literal
pool of the current section and sub-section.  At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.

Note - older versions of GAS would dump the current literal
pool any time a section change occurred.  This is no longer done, since
it prevents accurate control of the placement of literal pools.

@c MMMMMMMMMMMMMMMMMMMMMMMMMM

@c NNNNNNNNNNNNNNNNNNNNNNNNNN
@c OOOOOOOOOOOOOOOOOOOOOOOOOO

@c PPPPPPPPPPPPPPPPPPPPPPPPPP

@cindex @code{.pool} directive, AArch64
@item .pool
This is a synonym for .ltorg.

@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
@c RRRRRRRRRRRRRRRRRRRRRRRRRR

@cindex @code{.req} directive, AArch64
@item @var{name} .req @var{register name}
This creates an alias for @var{register name} called @var{name}.  For
example:

@smallexample
        foo .req w0
@end smallexample

ip0, ip1, lr and fp are automatically defined to
alias to X16, X17, X30 and X29 respectively.

@c SSSSSSSSSSSSSSSSSSSSSSSSSS

@c TTTTTTTTTTTTTTTTTTTTTTTTTT

@cindex @code{.tlsdescadd} directive, AArch64
@item   @code{.tlsdescadd}
Emits a TLSDESC_ADD reloc on the next instruction.

@cindex @code{.tlsdesccall} directive, AArch64
@item   @code{.tlsdesccall}
Emits a TLSDESC_CALL reloc on the next instruction.

@cindex @code{.tlsdescldr} directive, AArch64
@item   @code{.tlsdescldr}
Emits a TLSDESC_LDR reloc on the next instruction.

@c UUUUUUUUUUUUUUUUUUUUUUUUUU

@cindex @code{.unreq} directive, AArch64
@item .unreq @var{alias-name}
This undefines a register alias which was previously defined using the
@code{req} directive.  For example:

@smallexample
        foo .req w0
        .unreq foo
@end smallexample

An error occurs if the name is undefined.  Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'w0').  This
should only be done if it is really necessary.

@c VVVVVVVVVVVVVVVVVVVVVVVVVV

@cindex @code{.variant_pcs} directive, AArch64
@item .variant_pcs @var{symbol}
This directive marks @var{symbol} referencing a function that may
follow a variant procedure call standard with different register
usage convention from the base procedure call standard.

@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX

@cindex @code{.xword} directive, AArch64
@item .xword @var{expressions}
The @code{.xword} directive produces 64 bit values.  This is the same
as the @code{.dword} directive.

@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ

@cindex @code{.cfi_b_key_frame} directive, AArch64
@item	@code{.cfi_b_key_frame}
The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
corresponding to the current frame's FDE, meaning that its return address has
been signed with the B-key.  If two frames are signed with differing keys then
they will not share the same CIE.  This information is intended to be used by
the stack unwinder in order to properly authenticate return addresses.

@end table

@node AArch64 Opcodes
@section Opcodes

@cindex AArch64 opcodes
@cindex opcodes for AArch64
GAS implements all the standard AArch64 opcodes.  It also
implements several pseudo opcodes, including several synthetic load
instructions.

@table @code

@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
@item LDR =
@smallexample
  ldr <register> , =<expression>
@end smallexample

The constant expression will be placed into the nearest literal pool (if it not
already there) and a PC-relative LDR instruction will be generated.

@end table

For more information on the AArch64 instruction set and assembly language
notation, see @samp{ARMv8 Instruction Set Overview} available at
@uref{http://infocenter.arm.com}.


@node AArch64 Mapping Symbols
@section Mapping Symbols

The AArch64 ELF specification requires that special symbols be inserted
into object files to mark certain features:

@table @code

@cindex @code{$x}
@item $x
At the start of a region of code containing AArch64 instructions.

@cindex @code{$d}
@item $d
At the start of a region of data.

@end table