Age | Commit message (Collapse) | Author | Files | Lines |
|
* macl.s: New file.
* macw.s: New file.
* allinsn.exp: Add new tests for mac.w and mac.l.
|
|
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
correction for MAC.W handler
* sim/sh/interp.c ( macl ): New Function. Implementation of
MAC.L handler.
|
|
|
|
* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop
maintenance. List igen and sh maintainers. Mention that target
and global maintainers pick up the slack.
|
|
control the translation.
(m68hc11tim_print_timer): Update cycle_to_string conversion.
(m68hc11tim_timer_event): Fix handling of output
compare register with its interrupts.
(m68hc11tim_io_write_buffer): Check output compare
after setting M6811_TMSK1.
(m68hc11tim_io_read_buffer): Fix compilation warning.
* dv-m68hc11.c (m68hc11_option_handler): Likewise.
* dv-m68hc11spi.c (m68hc11spi_info): Likewise.
* dv-m68hc11sio.c (m68hc11sio_info): Likewise.
* interrupts.c (interrupts_info): Likewise.
(interrupts_reset): Recognize bootstrap mode.
* sim-main.h (PRINT_CYCLE, PRINT_TIME): New defines.
(_sim_cpu): Add cpu_start_mode.
(cycle_to_string): Add flags member.
* m68hc11_sim.c (OPTION_CPU_BOOTSTRAP): New option.
(cpu_options): Declare new option bootstrap.
(cpu_option_handler): Handle it.
(cpu_info): Update call to cycle_to_string.
|
|
the physical address in virtual address.
(struct _sim_cpu): Add memory bank members.
* m68hc11_sim.c (cpu_initialize): Clear memory bank parameters.
* interp.c (sim_hw_configure): Create memory bank according to memory
bank parameters.
(sim_get_bank_parameters): New function to obtain memory bank config
from the symbol table.
(sim_prepare_for_program): Call it to obtain the memory bank parameters.
(sim_open): Call sim_prepare_for_program.
* dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters
to check if address is within bank window.
(m68hc11cpu_io_read_buffer): Likewise.
(attach_m68hc11_regs): Map the memory bank according to memory bank
parameters.
|
|
|
|
* sim-main.h (print_io_word): Declare.
* dv-m68hc11tim.c (tmsk1_desc): New description table for TMSK1.
(tflg1_desc): Likewise for TFLG1.
(m68hc11tim_info): Print input and output compare registers
|
|
* gencode.c (expand_ppi_code): Comment spelling fix.
|
|
* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
* mova.s: Add dozens of new mova tests.
|
|
* compile.c (decode): Enhancements for mova.
Initialize cst, reg, and rdisp inside the loop, for each
new instruction. Defer correction of the disp2 values until
later, and then adjust them by the size of the first operand,
rather than the size of the instruction.
(sim_resume): For mova, adjust the size of the second operand
according to the type of the first operand (INDEXB vs. INDEXW).
In cases where there is only one operand, the other two must
both be composed on the fly.
|
|
* pshai.s, pshar.s, pshli.s, pshlr.s: New files.
* allinsn.exp: Add psha, pshl tests.
* pdec.s, pinc.s, padd.s, paddc.s: New files.
* allinsn.exp: Add pdec, pinc, padd, paddc tests.
* pand.s, pdmsb.s: New files.
* allinsn.exp: Add pand, pdmsb tests.
|
|
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
|
|
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
|
|
* gencode.c: Fix typo in comment.
|
|
* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
|
|
* gencode.c (prnd): Clear LSW of result to zeros.
|
|
* pmuls.s: New file.
|
|
* gencode.c (pmuls): Expression is mis-parenthesized.
|
|
* configure.in: Add testsuite to extra_subdirs for sh.
* configure: Regenerate.
|
|
* sim/sh: New directory. Tests for Renesas sh family.
|
|
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
|
|
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
condition is false, we want to return (not break). A break
will take us to the end of the function where registers will
be updated, whereas the desired outcome is for nothing to change.
|
|
* gencode.c (op tab): Some fix-ups of refs and defs.
(ocbi, ocbp): Cache not simulated, but may cause memory fault.
(gensym_caselist): Add default case to switch statement.
(expand_ppi_code): Add default case to switch statement.
|
|
* gencode.c (op tab): Implement movca.l.
|
|
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
|
|
* gencode.c (gensim_caselist): The movy instructions use
registers R6 and R7 (not R4 and R5 like the movx insns).
|
|
* compile.c (sim_resume): Revert 6-24 change, it does not
work with gdb breakpoints.
|
|
* compile.c (sim_resume): Handle shll reg, reg and shlr reg, reg.
|
|
* compile.c (decode): IMM16 is always zero-extended.
|
|
* gencode.c (movs): Fix a couple of text transpositions.
|
|
* sim-main.h (SIM_WIFSTOPPED, SIM_WSTOPSIG): Define.
* compile.c (sim_resume): Use the above to return stop signal.
|
|
* gencode.c (op movsxy_tab): Fix up some copy/paste errors
in name: s/REG_x/REG_y/.
|
|
* gencode.c (op tab): Move misplaced semicolon.
|
|
* nrun.c (main): Delete h8/300 ifdef (sim now handles signals).
|
|
* sim-reg.c: Fix cut-and-paste bug in comment.
|
|
Written by matthew green <mrg@redhat.com>, with fixes from Aldy
Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
Nick Clifton <nickc@redhat.com>.
* ppc-instructions: Include altivec.igen and e500.igen.
(model_busy, model_data): Add vr_busy and vscr_busy.
(model_trace_release): Trace vr_busy and vscr_busy.
(model_new_cycle): Update vr_busy and vscr_busy.
(model_make_busy): Update vr_busy and vscr_busy.
* registers.c (register_description): Add Altivec and e500
registers.
* psim.c (psim_read_register, psim_read_register): Handle Altivec
and e500 registers.
* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
* configure.in (sim_filter): When *altivec* add "av". When *spe*
or *simd* add e500.
(sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add
WITH_E500.
* configure: Re-generate.
* e500.igen, altivec.igen: New files.
* e500_expression.h, altivec_expression.h: New files.
* idecode_expression.h: Update copyright. Include
"e500_expression.h" and "altivec_expression.h".
* e500_registers.h, altivec_registers.h: New files.
* registers.h: Update copyright. Include "e500_registers.h" and
"altivec_registers.h".
(registers): Add Altivec and e500 specific registers.
* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
"idecode_altivec.h".
(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
(tmp-igen): Add dependencies on altivec.igen and e500.igen .
|
|
* interp.c (xfer_mem): Simplify. Only do a single partial
transfer. Problem reported by Tom Rix.
|
|
From matthew green <mrg@redhat.com>:
* sim-fpu.h: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New prototypes.
* sim-fpu.c: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New inline functions.
|
|
|
|
|
|
Problems reported by Joshua LeVasseur.
* emul_chirp.c: Update copyright.
(chirp_emul_nextprop): Return the first property.
* hw_htab.c: Update copyright.
(htab_decode_hash_table): Fix check for htab size.
|
|
* interrupts.c: Update copyright.
(external_interrupt): Fix test for already pending interrupt.
Problem found by Joshua LeVasseur.
|
|
* ppc-instructions: Add missing +8 line. Found by blofeldus at
yahoo.com.
|
|
From Ian Lance Taylor <ian@airs.com>:
* hw_nvram.c (hw_nvram_init_address): Correct call to memset--swap
second and third arguments.
|
|
* hw_com.c (hw_com_device_init_data): Check that the output, and
not input file opened. Pointed out by masahino tky3.3web.ne.jp.
|
|
* cgen-trace.h (sim_disasm_read_memory): Update args to be compatible
with disassemble_info:read_memory_func.
* cgen-trace.c (sim_disasm_read_memory): Ditto.
|
|
* sim_calls.c (sim_create_inferior): Assert that
psim_write_register succeeded.
(sim_fetch_register, sim_store_register): Make "regname" constant.
Delete Altivec hack. Return result from psim_read_register /
psim_write_register.
* psim.h (psim_read_register, psim_write_register): Change return
type to int. Update comments.
* psim.c: Update copyright.
(psim_stack): Assert that the psim_read_register worked.
(psim_read_register, psim_read_register): Return the register's
size. Allocate the cooked buffer dynamically.
* hw_register.c: Update copyright.
(do_register_init): Check that psim_write_register succeeded.
* hw_init.c: Update copyright.
(create_ppc_elf_stack_frame, create_ppc_aix_stack_frame): Assert
that the register transfer worked.
|
|
* ld-insn.h: Update copyright.
(cache_fields): Define.
(insn_table_fields): Add insn_field_6 and insn_field_7.
(load_insn_table): Pass in the "cache_rules".
* ld-insn.c: Update copyright.
(load_insn_table): Add parameter "cache_rules". Handle "cache",
"computed" and "scratch" fields.
(main): Pass "cache_rules" to load_insn_table.
* ld-cache.h: Update copyright.
(append_cache_table): Declare.
* ld-cache.c: Update copyright.
(append_cache_table): New function.
(load_cache_table): Call.
* gen-model.c: Include "ld-cache.h".
* gen-itable.c: Include "ld-cache.h".
* igen.c: Move #include "ld-cache.h" to earlier. Update
copyright.
(main): Permit a NULL "cache_rules". Pass address of
"cache_rules" to load_insn_table.
* Makefile.in (tmp-ld-insn): Add "ld-cache.o".
(tmp-igen): Do not include ppc-cache-rules.
(gen-itable.o, gen-model.o): Add "ld-cache.h".
* ppc-cache-rules: Delete file.
* ppc-instructions: Add cache rules.
|
|
* Makefile.in (ICACHE_CFLAGS, SEMANTICS_CFLAGS): Delete.
(SIM_FPU_FLAGS): Define.
(icache.o): Delete explicit compile command.
(semantics.o, idecode.o): Delete explicit compile command.
(NOWARN_CFLAGS, STD_CFLAGS): Append SIM_FPU_CFLAGS.
* gen-support.c (gen_support_c): Generate #include of
"sim-inline.h" and "sim-fpu.h", but conditional on
HAVE_COMMON_FPU.
* gen-idecode.c (gen_idecode_c): Ditto.
* igen.c (gen_icache_c, gen_semantics_c): Wrap #include of
"sim-inline.h" and "sim-fpu.h" in HAVE_COMMON_FPU conditional.
Move to before "support.h".
* Makefile.in, gen-support.c, gen-idecode.c, igen.c: Update
copyright.
|