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AgeCommit message (Expand)AuthorFilesLines
2000-10-24* pendanticismBen Elliston2-15/+17
2000-10-19* cleanupFrank Ch. Eigler2-5/+5
2000-10-08* usability improvementsBen Elliston3-0/+27
2000-10-062000-10-06 Dave Brolley <brolley@redhat.com>Dave Brolley4-3/+21
2000-10-062000-10-06 Dave Brolley <brolley@redhat.com>Dave Brolley3-2/+15
2000-09-262000-09-26 Dave Brolley <brolley@redhat.com>Dave Brolley2-0/+75
2000-09-15Replace StrongARM property with v4 and v5 properties.Nick Clifton6-90/+119
2000-09-12Missing Makefile.in for 68hc11 simulatorStephane Carrez2-0/+64
2000-09-10Remove soft reg hack in the 68hc11 simulatorStephane Carrez3-60/+8
2000-09-10Fix clearing of interrupts in 68hc11 simulatorStephane Carrez2-4/+21
2000-09-09 * sim-main.h: Define cycle_to_string.Stephane Carrez7-26/+70
2000-09-06Fix 68hc11 timer device (accuracy, io, timer overflow)Stephane Carrez2-115/+197
2000-09-05Fix 68HC11 SPI simulatorStephane Carrez2-8/+38
2000-08-282000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley11-181/+346
2000-08-282000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley3-78/+176
2000-08-282000-08-28 Dave Brolley <brolley@redhat.com>Dave Brolley2-1/+13
2000-08-22Forgot to check this in with last commit!Dave Brolley1-0/+15
2000-08-21* Contribute CGEN simulator build support code.Frank Ch. Eigler9-4/+325
2000-08-152000-08-15 Dave Brolley <brolley@redhat.com>Dave Brolley1-2/+2
2000-08-152000-08-15 Dave Brolley <brolley@redhat.com>Dave Brolley2-6/+103
2000-08-15Compute write back value for post increment loads beforeNick Clifton2-34/+47
2000-08-11Use address mapping levels for 68hc11 simulator (kill overlap hack)Stephane Carrez9-39/+67
2000-08-112000-08-10 Kazu Hirata <kazu@hxi.com>Kazu Hirata2-8/+10
2000-08-11Eliminate use of MIN().Andrew Cagney2-2/+7
2000-08-09* am33.igen: Warning clean-up.Alexandre Oliva2-42/+24
2000-07-27* Usability improvementFrank Ch. Eigler2-1/+6
2000-07-27Don't clean *.igen.Andrew Cagney2-1/+6
2000-07-272000-06-23 Doug Evans <dje@casey.transmeta.com>Andrew Cagney2-8/+10
2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney3-2/+9
2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney5-0/+39
2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2-1/+17
2000-07-27Add m68hc11 configry.Andrew Cagney5-0/+4366
2000-07-27New simulator.Andrew Cagney16-0/+7449
2000-07-27From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:Andrew Cagney4-2/+126
2000-07-27* compile.c (decode): Distinguish inc/dec.[wl] and adds/subsAndrew Cagney2-1/+11
2000-07-20* m16.igen (break): Call SignalException not sim_engine_halt.Andrew Cagney2-1/+5
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-1/+5
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-0/+9
2000-07-05Change minimum loop size limit to 0x10 (103792)Nick Clifton2-1/+5
2000-07-04* armvirt.c (ABORTS): Do not define.Alexandre Oliva2-1/+3
2000-07-04* armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva5-11/+59
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2-1/+3
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva4-45/+48
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2-2/+5
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva3-37/+48
2000-07-04* armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva3-4/+18
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva4-30/+40
2000-07-04* armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2-8/+20
2000-07-04* armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva3-8/+6
2000-07-04TIc80 simulator.Andrew Cagney18-1/+8613
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