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2011-03-25sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger3-10/+64
2011-03-25sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2-4/+16
2011-03-25sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2-0/+11
2011-03-24sim: bfin: document SIC limitationMike Frysinger2-1/+27
2011-03-24sim: bfin: fix inverted W1C logicMike Frysinger14-17/+34
2011-03-24sim: bfin: define more UART LSR bitsMike Frysinger2-7/+16
2011-03-24sim: bfin: fix typo in TWI stat regMike Frysinger2-1/+5
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2-2/+7
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2-0/+10
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2-6/+14
2011-03-24sim: bfin: fix thinko in SIC pin encodingMike Frysinger2-511/+516
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2-9/+5
2011-03-24sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2-30/+38
2011-03-21 * gennltvals.sh: Search sys/_default_fcntl.h, in addition toKevin Buettner5-384/+390
2011-03-21 * simops (OP_10007E0): Update errno handling as most trapsKevin Buettner2-3/+88
2011-03-17sim: bfin: check for kill/preadMike Frysinger5-2/+25
2011-03-15sim: bfin: add GPIO device simulationMike Frysinger7-28/+369
2011-03-15sim: bfin: fix brace styleMike Frysinger27-27/+54
2011-03-15sim: bfin: fix brace styleMike Frysinger58-161/+342
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2-1/+6
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2-6/+10
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2-8/+40
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2-7/+15
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger2-34/+79
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger2-0/+6
2011-03-15sim: common: trim trailing whitespaceMike Frysinger42-292/+300
2011-03-14sim: bfin: forgot to cvs add the changelogMike Frysinger1-0/+29
2011-03-06sim: bfin: new portMike Frysinger108-0/+30271
2011-02-25 * callback.c (fdbad): Return EBADF rather than EINVAL for badKevin Buettner2-1/+6
2011-02-14sim: punt zfree()Mike Frysinger46-125/+185
2011-02-14sim: change to 64bit time keeping to avoid 32bit overflowsMike Frysinger2-1/+5
2011-01-12sim: enable hw_tree_delete in sim_hw_uninstallMike Frysinger2-1/+5
2011-01-12sim: check asprintf return valuesMike Frysinger5-6/+29
2011-01-11sim: allow memory maps to default to mapped filesMike Frysinger2-10/+38
2011-01-11http://sourceware.org/ml/gdb-patches/2010-11/msg00112.htmlAndrew Burgess14-10/+45
2011-01-10sim: fix handling of 2nd arg to SIM_AC_OPTION_HARDWAREMike Frysinger2-3/+9
2011-01-10sim: add noreturn markings to more hw abort/halt funcsMike Frysinger3-4/+9
2011-01-05 * testutils.inc: Correct comment syntax fallout fromHans-Peter Nilsson5-8/+12
2011-01-05 * mips32-dsp.s: Update copyright year.Hans-Peter Nilsson2-1/+5
2011-01-05sim: ignore generated hw-config.hMike Frysinger2-0/+5
2011-01-05sim: tweak load buffer type to avoid signed warningsMike Frysinger2-1/+5
2011-01-05Copyright year update in sim/ppc/psim.texinfoJoel Brobecker2-2/+6
2011-01-05Update the copyright year for most remaining files in GDBJoel Brobecker2-1/+5
2011-01-01run copyright.sh for 2011.Joel Brobecker343-350/+464
2010-12-29sim: HW_NALLOC: new alloc helperMike Frysinger2-0/+5
2010-12-29sim: HW_NZALLOC: fix arg handlingMike Frysinger2-1/+5
2010-12-23sim: start a gitignoreMike Frysinger2-0/+11
2010-12-15sim: add --map-info optionMike Frysinger2-1/+50
2010-12-14(decode_opcode): RXO_branchrel is relative to the opcode's PC, notDJ Delorie2-2/+4
2010-12-14* rx.c (decode_opcode): For "MVFC PC,", use the address of theDJ Delorie2-0/+13
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