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AgeCommit message (Expand)AuthorFilesLines
2022-12-23sim: lm32/m32r: drop redundant opcode/cgen.h includeMike Frysinger2-2/+0
2022-12-23sim: ppc: drop unused types from sim-main.hMike Frysinger1-7/+0
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger10-5/+9
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger8-7/+2
2022-12-23Revert "sim: mn10300: drop unused sim-main.c"Mike Frysinger1-0/+9
2022-12-22sim: mn10300: drop unused sim-main.cMike Frysinger1-4/+0
2022-12-22sim: endian: move bfd.h from header to sourceMike Frysinger2-2/+2
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger20-13/+16
2022-12-22sim: mcore: replace custom "word" type with int32_tMike Frysinger2-33/+30
2022-12-22sim: moxie: replace custom "word" type with int32_tMike Frysinger1-13/+11
2022-12-22sim: cr16/d10v/mcore/moxie: clean up unused word & uword typesMike Frysinger4-10/+0
2022-12-22sim: mips: trim redundant igen settingsMike Frysinger2-18/+0
2022-12-22sim: mips: merge mips64* with existing multi-run buildMike Frysinger2-10/+4
2022-12-22sim: mips: merge mips64vr5000 with existing multi-run buildMike Frysinger2-8/+2
2022-12-22sim: mips: switch from SIM_ADDR to address_wordMike Frysinger2-31/+13
2022-12-22sim: v850: switch from SIM_ADDR to address_wordMike Frysinger2-4/+4
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger13-58/+60
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger11-12/+12
2022-12-22sim: m32r: include sim-hw.h for sim_hw_parseMike Frysinger1-0/+1
2022-12-22sim: mips: merge mips64vr4300 with existing multi-run buildMike Frysinger2-8/+2
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger8-71/+44
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger8-99/+48
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger8-43/+68
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
2022-12-21sim: hw-config.h: move generation to top-levelMike Frysinger3-30/+54
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger16-127/+190
2022-12-21sim: build: hoist lists of common objects upMike Frysinger4-131/+167
2022-12-21sim: fully merge sim_cpu_base into sim_cpuMike Frysinger1-26/+19
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger29-66/+1
2022-12-21sim: or1k: invert sim_cpu storageMike Frysinger5-30/+43
2022-12-21sim: m32r: invert sim_cpu storageMike Frysinger5-14/+10
2022-12-21sim: lm32: invert sim_cpu storageMike Frysinger3-12/+7
2022-12-21sim: iq2000: invert sim_cpu storageMike Frysinger3-11/+7
2022-12-21sim: frv: invert sim_cpu storageMike Frysinger3-23/+18
2022-12-21sim: cris: invert sim_cpu storageMike Frysinger6-239/+244
2022-12-21sim: bpf: invert sim_cpu storageMike Frysinger3-7/+13
2022-12-21sim: cgen: prep for inverting sim_cpu storageMike Frysinger2-0/+15
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-21sim: pru: invert sim_cpu storageMike Frysinger3-8/+31
2022-12-21sim: example-synacor: invert sim_cpu storageMike Frysinger3-37/+47
2022-12-21sim: h8300: invert sim_cpu storageMike Frysinger2-34/+36
2022-12-21sim: m68hc11: invert sim_cpu storageMike Frysinger10-354/+446
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger3-20/+23
2022-12-21sim: mcore: invert sim_cpu storageMike Frysinger2-27/+41
2022-12-21sim: aarch64: invert sim_cpu storageMike Frysinger5-108/+152
2022-12-21sim: microblaze: invert sim_cpu storageMike Frysinger3-8/+8
2022-12-21sim: avr: invert sim_cpu storageMike Frysinger2-99/+108
2022-12-21sim: moxie: invert sim_cpu storageMike Frysinger2-14/+13
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