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AgeCommit message (Expand)AuthorFilesLines
2021-05-08sim: h8300: clean up various warningsMike Frysinger4-8/+21
2021-05-08sim: touch modules targetMike Frysinger2-0/+5
2021-05-08sim: cgen: tweak trace formatMike Frysinger2-1/+5
2021-05-08sim: cgen: namespace mode_names a bitMike Frysinger3-3/+11
2021-05-08sim: cgen: tweak cgen_rtx_error to fix warningsMike Frysinger3-1/+8
2021-05-08sim: cgen: tweak initializers to avoid warningsMike Frysinger2-6/+10
2021-05-08sim: add html & pdf stubsMike Frysinger2-0/+13
2021-05-08sim: use htab_eq_stringTom Tromey2-9/+6
2021-05-07sim: m68hc11: fix up cycle buffer printingMike Frysinger2-5/+8
2021-05-07sim: Add bfd include path for common testsuite toolsDimitar Dimitrov4-2/+12
2021-05-07sim: m32c: clean up various warningsMike Frysinger5-21/+41
2021-05-07sim: m32c: fix warnings about mixing code & declsMike Frysinger3-1/+31
2021-05-07sim: m32c: switch from custom fgets to getlineMike Frysinger5-105/+17
2021-05-06sim: m68hc11: fix up last warningsMike Frysinger4-105/+113
2021-05-06sim: m68hc11: warn when emul_write failsMike Frysinger2-2/+10
2021-05-06sim: h8300 special case testYoshinori Sato4-2/+37
2021-05-05sim: m32c/rl78/rx: fix command parsingMike Frysinger6-80/+59
2021-05-04sim: rl78: clean up various warningsMike Frysinger9-17/+34
2021-05-04sim: m68hc11: tweak types to fix warningsMike Frysinger3-2/+7
2021-05-04sim: mips: include stdlib.h for memory prototypesMike Frysinger2-0/+5
2021-05-04sim: mips: always enable device modelsMike Frysinger3-18/+8
2021-05-04sim: mips: delete unused constant variablesMike Frysinger4-29/+10
2021-05-04sim: mcore: fix build time warningsMike Frysinger4-3/+11
2021-05-04sim: remove sys/times.h in most placesMike Frysinger6-3/+12
2021-05-04sim: mips: fix qh_acc tableMike Frysinger2-1/+5
2021-05-04sim: hw: localize init callbackMike Frysinger4-14/+13
2021-05-04sim: microblaze: enable some basic trace pointsMike Frysinger3-0/+9
2021-05-04sim: microblaze: hook up libgloss syscallsMike Frysinger6-4/+54
2021-05-04Add missing stdlib.h includes to simTom Tromey10-0/+26
2021-05-04Fix igen buildTom Tromey3-0/+8
2021-05-04Add config.h to generated_files for simTom Tromey2-0/+5
2021-05-04sim: add support for build-time ar & ranlibMike Frysinger68-66/+476
2021-05-04sim: clean up bfd_vma printingMike Frysinger18-42/+79
2021-05-03sim: add ATTRIBUTE_PRINTF / ATTRIBUTE_NULL_PRINTF where necessarySimon Marchi17-21/+50
2021-05-02sim: add default cases to two switches in sim-options.cSimon Marchi2-0/+7
2021-05-02sim: replace custom attributes with ansidecl.hMike Frysinger20-63/+79
2021-05-01sim: bfin: move option inits to respective modulesMike Frysinger4-13/+30
2021-05-01sim: options: fix --help outputMike Frysinger2-0/+5
2021-05-01sim: dv-sockser: localize init callbackMike Frysinger4-12/+12
2021-05-01sim: mips: mark local func staticMike Frysinger2-1/+5
2021-05-01sim: add framework for declaring init callbacks locallyMike Frysinger4-16/+74
2021-05-01sim: nrun: add local strsignal prototypeMike Frysinger97-62/+386
2021-05-01sim: rx: cast bfd_vma when printingMike Frysinger2-1/+5
2021-05-01sim: riscv: fix building on 32-bit hosts w/out int128Mike Frysinger2-1/+5
2021-05-01sim: aarch64: use PRIx64 for formatting 64-bit typesMike Frysinger2-5/+12
2021-05-01sim: aarch64: fix 64-bit immediate shiftsMike Frysinger2-2/+6
2021-05-01sim: arm: move build logic to source filesMike Frysinger3-9/+25
2021-05-01sim: callback: inline wrap helperMike Frysinger2-25/+66
2021-04-26sim: riscv: switch MIN/MAX to common min/maxMike Frysinger2-7/+9
2021-04-26sim: nltvals: unify common syscall tablesMike Frysinger29-508/+117
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