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AgeCommit message (Expand)AuthorFilesLines
2017-06-02Correct check for endiannessMichael Eager2-1/+5
2017-05-24Refactor disassembler selectionYao Qi2-1/+9
2017-04-22Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson14-202/+454
2017-04-08Add support for fcvtl and fcvtl2.Jim Wilson4-0/+112
2017-04-08Support the fcmXX zero instructions.Jim Wilson4-0/+232
2017-03-25Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson4-1/+27
2017-03-03Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson5-9/+89
2017-02-25Add missing smov support, and clean up existing umov support.Jim Wilson4-75/+227
2017-02-25Add missing cnt (popcount) instruction support.Jim Wilson4-0/+94
2017-02-19Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson8-36/+157
2017-02-14Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson6-49/+128
2017-02-14Fix bit/bif instructions.Jim Wilson4-10/+107
2017-02-14Add ldn/stn single support, fix ldnr support.Jim Wilson6-269/+698
2017-02-13sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger39-62/+141
2017-01-23Add support for cmtst.Jim Wilson4-0/+113
2017-01-17Fixes for addv and xtn2 instructions.Jim Wilson5-31/+158
2017-01-09Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson4-17/+273
2017-01-04Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson9-33/+618
2017-01-01update copyright year range in GDB filesJoel Brobecker576-576/+576
2016-12-21Fix bugs with float compare and Inf operands.Jim Wilson4-0/+184
2016-12-14MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2-0/+6
2016-12-13Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson7-45/+309
2016-12-03Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2-3/+8
2016-12-01Fix typo in ChangeLog entry.Jim Wilson1-1/+1
2016-12-01Fix bug with FP stur instructions.Jim Wilson2-6/+11
2016-11-12sim: mips: add PR info to ChangeLogMike Frysinger1-0/+2
2016-11-11sim: mips: fix dv-tx3904cpu build errorMike Frysinger2-0/+10
2016-11-11sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2-0/+5
2016-10-18sim: avr: move changelog entries to subdirMike Frysinger2-7/+7
2016-08-16sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2-25/+34
2016-08-15sim: unify symbol table handlingMike Frysinger17-170/+164
2016-08-13sim: m68hc11: standardize sim_cpu namingMike Frysinger10-347/+366
2016-08-13sim: m68hc11: fix up various prototype related warningsMike Frysinger8-12/+29
2016-08-13sim: cgen: constify mode_namesMike Frysinger3-2/+7
2016-08-13sim: cgen: drop unused argv/envp definitionsMike Frysinger2-8/+5
2016-08-13sim: bfin: split out common mach/model defines into arch.h [PR sim/20438]Mike Frysinger4-26/+55
2016-08-12Undo the previous change to the aarch64 sim - exporting aarch64_step() - and ...Nick Clifton3-9/+19
2016-08-11Export the single step function from the AArch64 simulator.Nick Clifton4-9/+19
2016-07-27Wean gdb and sim off private libbfd.h headerAlan Modra6-7/+18
2016-07-21Fix typo fsqrt -> sqrtf.Nick Clifton1-1/+1
2016-07-21Use fsqrt() to calculate float (rather than double) square root.Nick Clifton2-1/+5
2016-07-19 Update PC when simulate break instruction.Denis Chertykov2-2/+8
2016-07-14Small improvements to the ARM simulator to cope with illegal binaries.Nick Clifton3-4/+13
2016-06-30Add support for simulating big-endian AArch64 binaries.Jim Wilson3-9/+30
2016-05-06Add support for FMLA (by element) to AArch64 sim.Nick Clifton2-2/+77
2016-04-27Fix a typo in the check for SNANs in the RX simulator.Nick Clifton2-1/+7
2016-04-27Add support for the --trace-decode option to the AArch64 simulator.Nick Clifton2-7/+317
2016-04-10Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.Oleg Endo3-37/+21
2016-04-10Move ChangeLog entries from sim/ChangeLog to sim/sh/ChangeLog.Oleg Endo2-5/+5
2016-04-09Adjust default memory size and stack base address for SH simulator.Oleg Endo2-3/+8
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