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AgeCommit message (Expand)AuthorFilesLines
2021-05-17sim: fully merge sim_state_base into sim_stateMike Frysinger43-93/+154
2021-05-17sim: riscv: invert sim_state storageMike Frysinger4-12/+22
2021-05-17sim: h8300: invert sim_state storageMike Frysinger3-11/+32
2021-05-17sim: mips: invert sim_state storageMike Frysinger5-27/+27
2021-05-17sim: avr: invert sim_state storageMike Frysinger3-11/+23
2021-05-17sim: cgen: invert sim_state storage for cgen portsMike Frysinger17-74/+49
2021-05-17sim: bfin: invert sim_state storageMike Frysinger3-9/+12
2021-05-17sim: invert sim_state storageMike Frysinger33-124/+143
2021-05-16sim: install library header filesMike Frysinger3-37/+78
2021-05-16sim: switch config.h usage to defs.hMike Frysinger302-169/+923
2021-05-16sim: riscv: move __int128 check to configureMike Frysinger96-63/+596
2021-05-15sim: ppc: clean up various warningsMike Frysinger22-54/+122
2021-05-15sim: switch to libiberty environ.hMike Frysinger4-24/+18
2021-05-14sim: callback: convert FS interfaces to 64-bitMike Frysinger4-8/+16
2021-05-14sim: callback: convert time interface to 64-bitMike Frysinger9-21/+35
2021-05-14sim: callback: inline PTR defineMike Frysinger3-3/+8
2021-05-14sim: create header namespaceMike Frysinger70-74/+190
2021-05-12sim: clean up explicit environment build callsMike Frysinger8-48/+16
2021-05-12Fix build failure in d10v simLuis Machado2-2/+11
2021-05-08sim: h8300: clean up various warningsMike Frysinger4-8/+21
2021-05-08sim: touch modules targetMike Frysinger2-0/+5
2021-05-08sim: cgen: tweak trace formatMike Frysinger2-1/+5
2021-05-08sim: cgen: namespace mode_names a bitMike Frysinger3-3/+11
2021-05-08sim: cgen: tweak cgen_rtx_error to fix warningsMike Frysinger3-1/+8
2021-05-08sim: cgen: tweak initializers to avoid warningsMike Frysinger2-6/+10
2021-05-08sim: add html & pdf stubsMike Frysinger2-0/+13
2021-05-08sim: use htab_eq_stringTom Tromey2-9/+6
2021-05-07sim: m68hc11: fix up cycle buffer printingMike Frysinger2-5/+8
2021-05-07sim: Add bfd include path for common testsuite toolsDimitar Dimitrov4-2/+12
2021-05-07sim: m32c: clean up various warningsMike Frysinger5-21/+41
2021-05-07sim: m32c: fix warnings about mixing code & declsMike Frysinger3-1/+31
2021-05-07sim: m32c: switch from custom fgets to getlineMike Frysinger5-105/+17
2021-05-06sim: m68hc11: fix up last warningsMike Frysinger4-105/+113
2021-05-06sim: m68hc11: warn when emul_write failsMike Frysinger2-2/+10
2021-05-06sim: h8300 special case testYoshinori Sato4-2/+37
2021-05-05sim: m32c/rl78/rx: fix command parsingMike Frysinger6-80/+59
2021-05-04sim: rl78: clean up various warningsMike Frysinger9-17/+34
2021-05-04sim: m68hc11: tweak types to fix warningsMike Frysinger3-2/+7
2021-05-04sim: mips: include stdlib.h for memory prototypesMike Frysinger2-0/+5
2021-05-04sim: mips: always enable device modelsMike Frysinger3-18/+8
2021-05-04sim: mips: delete unused constant variablesMike Frysinger4-29/+10
2021-05-04sim: mcore: fix build time warningsMike Frysinger4-3/+11
2021-05-04sim: remove sys/times.h in most placesMike Frysinger6-3/+12
2021-05-04sim: mips: fix qh_acc tableMike Frysinger2-1/+5
2021-05-04sim: hw: localize init callbackMike Frysinger4-14/+13
2021-05-04sim: microblaze: enable some basic trace pointsMike Frysinger3-0/+9
2021-05-04sim: microblaze: hook up libgloss syscallsMike Frysinger6-4/+54
2021-05-04Add missing stdlib.h includes to simTom Tromey10-0/+26
2021-05-04Fix igen buildTom Tromey3-0/+8
2021-05-04Add config.h to generated_files for simTom Tromey2-0/+5
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