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2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker577-577/+577
2015-12-30sim: m68hc11: fix default endianMike Frysinger3-2/+7
2015-12-30sim: cris/m68hc11: move default endian/alignment to configureMike Frysinger8-14/+115
2015-12-30sim: h8300: inline sim_state_initializeMike Frysinger2-27/+7
2015-12-30sim: h8300: simplify h8300_reg_{fetch,store} funcsMike Frysinger2-53/+29
2015-12-30sim: h8300: switch to common sim-resumeMike Frysinger3-40/+57
2015-12-30sim: h8300: move default endian/alignment to configureMike Frysinger4-6/+112
2015-12-30sim: simplify STATE_MY_NAME setupMike Frysinger2-3/+6
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger20-86/+169
2015-12-30sim: h8300: move unused/buggy lregs arrayMike Frysinger2-4/+5
2015-12-30sim: h8300: drop unused inst.hMike Frysinger3-104/+5
2015-12-29sim: ppc: track closed state of file descriptors 0, 1, and 2.Kevin Buettner3-22/+151
2015-12-27sim: aarch64/msp430: fix disassembler usageMike Frysinger4-4/+14
2015-12-27sim: unify sim-hloadMike Frysinger46-67/+93
2015-12-26sim: punt WITH_DEVICES & tconfig.h supportMike Frysinger95-290/+197
2015-12-26sim: bfin: push down mmr address/size checksMike Frysinger33-229/+549
2015-12-26sim: bfin: avoid stack error under asanMike Frysinger2-1/+5
2015-12-26sim: sim-core: pass down cpu to hw accesses when availableMike Frysinger2-10/+41
2015-12-26sim: mips: delete mmu stubs to move to common sim_{read,write}Mike Frysinger6-355/+153
2015-12-26sim: cris: do not pass cpu when writing memory during initMike Frysinger2-5/+10
2015-12-26sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger18-34/+106
2015-12-26sim: aarch64: move ChangeLog contentMike Frysinger2-26/+25
2015-12-25sim: frv: punt WITH_DEVICE supportMike Frysinger6-95/+10
2015-12-25sim: m32r: migrate from WITH_DEVICES to WITH_HWMike Frysinger12-178/+361
2015-12-25sim: cris: migrate from WITH_DEVICES to WITH_HWMike Frysinger10-126/+113
2015-12-25sim: cris: clean up rvdummy a bitMike Frysinger2-2/+6
2015-12-25sim: cris: set up sane default path to rvdummyMike Frysinger2-1/+14
2015-12-25sim: hw-properties: delete trace callsMike Frysinger2-4/+8
2015-12-25sim: drop WITH_ENGINE defineMike Frysinger3-15/+5
2015-12-25sim: sim-model: build for everyoneMike Frysinger29-49/+75
2015-12-25sim: move MACH/MODEL types into SIM_xxx namespaceMike Frysinger33-116/+172
2015-12-25sim: arm: delete unused codeMike Frysinger23-3651/+34
2015-12-25sim: move WITH_SCACHE_PBB to sim-main.hMike Frysinger18-49/+57
2015-12-25sim: device_error: puntMike Frysinger12-52/+32
2015-12-25sim: always enable callback memoryMike Frysinger4-13/+13
2015-12-25sim: dv-pal: always use CPU_INDEXMike Frysinger2-5/+7
2015-12-24sim: mips: delete TARGET_TX3904 defineMike Frysinger3-2/+5
2015-12-24sim: mips: move SIM_QUIET_NAN_NEGATED to sim-main.hMike Frysinger3-4/+8
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger25-42/+72
2015-12-24sim: cris: move option install to sim_openMike Frysinger5-19/+18
2015-12-24sim: delete old breakpoint codeMike Frysinger11-83/+26
2015-12-24sim: h8300: move h8300-specific options out of common codeMike Frysinger5-34/+69
2015-12-24sim: enable watchpoint module everywhereMike Frysinger18-35/+37
2015-12-24sim: delete SIM_HAVE_FLATMEM supportMike Frysinger6-54/+13
2015-12-24sim: delete SIM_HAVE_MEM_SIZEMike Frysinger8-28/+16
2015-12-24sim: delete SIM_HAVE_SIMCACHEMike Frysinger6-18/+12
2015-12-15Fix invalid left shift of negative valueDominik Vogt11-33/+55
2015-12-15Add support for the MRS instruction to the AArch64 simulator.Nick Clifton2-9/+53
2015-12-07Add support for MSP430 F5 hardware multiply.Nick Clifton2-10/+59
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton23-4/+31400
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