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path: root/sim/v850/v850.igen
AgeCommit message (Expand)AuthorFilesLines
2012-03-29Commit gdb and sim support for v850e2 and v850e2v3 on behalf ofKevin Buettner1-10/+2069
2008-02-06* simops.c (OP_1C007E0): Compensate for 64 bit hosts.DJ Delorie1-2/+2
2008-02-06Index: ChangeLogDJ Delorie1-18/+18
2003-09-05Add support for v850e1 instructionsNick Clifton1-0/+62
2003-04-06* simops.c (OP_40): Delete. Move code to...Nick Clifton1-1/+42
2002-09-19Remove v850ea referencesNick Clifton1-316/+0
2000-05-30Remove illegal instruciton pattern, since it is the same as the breakpointNick Clifton1-7/+0
2000-05-08* merge from internal treeFrank Ch. Eigler1-4/+15
2000-03-25* more compatibility with v850 hardwareFrank Ch. Eigler1-0/+7
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1407
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1461/+0
1997-12-05Reverrt BREAK value back to its old valueNick Clifton1-1/+1
1997-12-04Fixed sanitization,Nick Clifton1-208/+64
1997-09-19Clean up tracing for Bcond & jmp insns.Andrew Cagney1-128/+100
1997-09-19Fix cmov immed.Andrew Cagney1-12/+56
1997-09-19Fix cmov insn.Andrew Cagney1-1/+3
1997-09-17Clean up more tracing.Andrew Cagney1-3/+21
1997-09-17Fix tracing for: "ctret", "bsw", "hsw"Andrew Cagney1-36/+72
1997-09-16Smooth some of ALU tracing's rough edges.Andrew Cagney1-39/+69
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney1-2/+16
1997-09-16Add v850e version of breakpoint instruction.Andrew Cagney1-5/+16
1997-09-15For instructions moved into v850.igen was computing (wrong) NIA whenAndrew Cagney1-10/+10
1997-09-15Fix sanitization for v850 V v850e V v850eqAndrew Cagney1-11/+267
1997-09-15For v850eq start up with US bit set.Andrew Cagney1-2/+26
1997-09-12Check reserved bits before executing instructions.Andrew Cagney1-1/+48
1997-09-08Add multi-sim support to v850/v850e/v850eq simulators.Andrew Cagney1-0/+1151
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