Age | Commit message (Collapse) | Author | Files | Lines |
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* addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s,
bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s,
das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s,
mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s,
not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s,
shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s,
xorb.s, xorw.s, xorl.s: New files.
* allinsn.exp: New file.
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* configure.in: Add testsuite to extra_subdirs.
* configure: Regenerate.
2003-04-13 Michael Snyder <msnyder@redhat.com>
* sim/h8300: New directory. Tests for Hitachi h8/300 family.
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* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
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* lib/sim-defs.exp (run_sm_test): Correct comment. "output" and
"xerror" options do not use a list of machines. Clear options from
previous test case. Use "$cpu_option" to identify the machine to the
assembler, if specified.
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instead of sim_trace() to run the program; include support for ``-o''
option (operating environment); when a signal occurs, only continue
execution when operating environment mode.
Update d10v.
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* t-sadd.s: New file.
* Makefile.in (TESTS): Add t-sadd.
PR 18438.
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1999-01-11 Frank Ch. Eigler <fche@cygnus.com>
* do-flags.S: New test for parallel PSW update conflicts.
* Makefile.in (TESTS): Run it.
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1999-01-07 Frank Ch. Eigler <fche@cygnus.com>
* do-2wordops.S: New test for sign-extension by ld2h.
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1998-12-31 Frank Ch. Eigler <fche@cygnus.com>
* sim/sky/t-cop2.s: Adjust vmtir instruction tests for new syntax.
* sim/sky/t-cop2.vuexpect: Matching changes.
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* sim/sky/mload.exp: ditto.
* sim/sky/sky_sce.exp: ditto.
* sim/sky/sky_sce_accurate.exp: ditto.
* sim/sky/sky_sce_fast.exp: ditto.
* sim/sky/mload.exp: mark as unresolved on error.
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* sim/fr30/ldres.cgs: New testcase.
* sim/fr30/stres.cgs: New testcase.
* sim/fr30/copop.cgs: New testcase.
* sim/fr30/copld.cgs: New testcase.
* sim/fr30/copst.cgs: New testcase.
* sim/fr30/copsv.cgs: New testcase.
* sim/fr30/nop.cgs: New testcase.
* sim/fr30/andccr.cgs: New testcase.
* sim/fr30/orccr.cgs: New testcase.
* sim/fr30/addsp.cgs: New testcase.
* sim/fr30/stilm.cgs: New testcase.
* sim/fr30/extsb.cgs: New testcase.
* sim/fr30/extub.cgs: New testcase.
* sim/fr30/extsh.cgs: New testcase.
* sim/fr30/extuh.cgs: New testcase.
* sim/fr30/enter.cgs: New testcase.
* sim/fr30/leave.cgs: New testcase.
* sim/fr30/xchb.cgs: New testcase.
* sim/fr30/dmovb.cgs: New testcase.
* sim/fr30/dmov.cgs: New testcase.
* sim/fr30/dmovh.cgs: New testcase.
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* sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
* sim/fr30/ret.cgs: Add tests fir ret:d.
* sim/fr30/inte.cgs: New testcase.
* sim/fr30/reti.cgs: New testcase.
* sim/fr30/bra.cgs: New testcase.
* sim/fr30/bno.cgs: New testcase.
* sim/fr30/beq.cgs: New testcase.
* sim/fr30/bne.cgs: New testcase.
* sim/fr30/bc.cgs: New testcase.
* sim/fr30/bnc.cgs: New testcase.
* sim/fr30/bn.cgs: New testcase.
* sim/fr30/bp.cgs: New testcase.
* sim/fr30/bv.cgs: New testcase.
* sim/fr30/bnv.cgs: New testcase.
* sim/fr30/blt.cgs: New testcase.
* sim/fr30/bge.cgs: New testcase.
* sim/fr30/ble.cgs: New testcase.
* sim/fr30/bgt.cgs: New testcase.
* sim/fr30/bls.cgs: New testcase.
* sim/fr30/bhi.cgs: New testcase.
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PR 18402
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* sim/m32r/uread32.ms: New testcase.
* sim/m32r/uwrite16.ms: New testcase.
* sim/m32r/uwrite32.ms: New testcase.
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* sim/m32r/hello.ms: Ditto.
* sim/m32r/hw-trap.ms: Ditto.
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errors. Translate \n sequences in expected output to newline char.
(slurp_options): Make parentheses optional.
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* sim/fr30/call.cgs: Test ret here as well.
* sim/fr30/ld.cgs: Remove bogus comment.
* sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
* sim/fr30/div.ms: New testcase.
* sim/fr30/st.cgs: New testcase.
* sim/fr30/sth.cgs: New testcase.
* sim/fr30/stb.cgs: New testcase.
* sim/fr30/mov.cgs: New testcase.
* sim/fr30/jmp.cgs: New testcase.
* sim/fr30/ret.cgs: New testcase.
* sim/fr30/int.cgs: New testcase.
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* sim/fr30/div0s.cgs: New testcase.
* sim/fr30/div0u.cgs: New testcase.
* sim/fr30/div1.cgs: New testcase.
* sim/fr30/div2.cgs: New testcase.
* sim/fr30/div3.cgs: New testcase.
* sim/fr30/div4s.cgs: New testcase.
* sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
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* sim/fr30/testutils.inc (set_s_user): Correct Mask.
(set_s_system): Correct Mask.
* sim/fr30/ld.cgs (ld): Move previously failing test back
into place.
* sim/fr30/ldm0.cgs: New testcase.
* sim/fr30/ldm1.cgs: New testcase.
* sim/fr30/stm0.cgs: New testcase.
* sim/fr30/stm1.cgs: New testcase.
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* sim/fr30/ldm0.cgs: New testcase.
* sim/fr30/ldm1.cgs: New testcase.
* sim/fr30/stm0.cgs: New testcase.
* sim/fr30/stm1.cgs: New testcase.
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* sim/fr30/testutils.inc (set_s_user): Correct Mask.
(set_s_system): Correct Mask.
* sim/fr30/ld.cgs (ld): Move previously failing test back
into place.
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1998-12-08 Frank Ch. Eigler <fche@cygnus.com>
* do-2wordops.S: New test for double-word load-like operations.
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