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AgeCommit message (Expand)AuthorFilesLines
2017-04-22Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson12-14/+341
2017-04-08Add support for fcvtl and fcvtl2.Jim Wilson2-0/+61
2017-04-08Support the fcmXX zero instructions.Jim Wilson2-0/+81
2017-03-25Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2-0/+21
2017-03-03Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson3-5/+68
2017-02-25Add missing smov support, and clean up existing umov support.Jim Wilson2-0/+93
2017-02-25Add missing cnt (popcount) instruction support.Jim Wilson2-0/+37
2017-02-19Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson6-19/+126
2017-02-14Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2-0/+105
2017-02-14Fix bit/bif instructions.Jim Wilson2-0/+93
2017-02-14Add ldn/stn single support, fix ldnr support.Jim Wilson4-0/+404
2017-01-23Add support for cmtst.Jim Wilson2-0/+108
2017-01-17Fixes for addv and xtn2 instructions.Jim Wilson3-0/+134
2017-01-09Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2-0/+218
2017-01-04Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson6-0/+547
2017-01-01update copyright year range in GDB filesJoel Brobecker20-20/+20
2016-12-21Fix bugs with float compare and Inf operands.Jim Wilson2-0/+150
2016-12-13Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson5-9/+288
2016-01-10sim: drop --enable-sim-cflags optionMike Frysinger2-5/+4
2016-01-06Change copyright owner to FSF in sim/testsuite/sim/mips/hilo-hazard-4.sJoel Brobecker2-2/+5
2016-01-05Fix the execution of the MSP430 simulator testsuite.Nick Clifton2-2/+38
2016-01-04sim: parse_args: polish getopt error messageMike Frysinger3-2/+7
2016-01-03sim: convert to bfd_endianMike Frysinger2-1/+6
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker19-19/+19
2015-12-25sim: cris: migrate from WITH_DEVICES to WITH_HWMike Frysinger2-1/+5
2015-12-25sim: cris: set up sane default path to rvdummyMike Frysinger2-1/+14
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger3-1/+25
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton6-0/+105
2015-11-15sim: mcore: add a fail testcaseMike Frysinger3-1/+14
2015-11-15sim: m32c: add a basic testsuiteMike Frysinger5-0/+92
2015-11-15sim: testsuite: support basic vars in flagsMike Frysinger2-1/+12
2015-11-10sim: m32c: move test code to testsuiteMike Frysinger6-0/+167
2015-10-12sim: ft32: test coverage for link parameters and PM write portJames Bowman2-0/+42
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger2-0/+22
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett4-6/+77
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu7-25/+25
2015-04-13Do unset_currtarget_info ldscript for all simulator testsuites.Hans-Peter Nilsson4-6/+18
2015-04-05sim: moxie: fix running after nrun conversionMike Frysinger4-0/+71
2015-04-05sim: mn10300: add a basic testsuiteMike Frysinger4-0/+88
2015-04-05sim: m68hc11: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: iq2000: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: lm32: add a basic testsuiteMike Frysinger4-0/+84
2015-03-30sim: d10v: convert to nrunMike Frysinger2-1/+5
2015-03-30sim: d10v: link in missing testsuiteMike Frysinger3-3/+16
2015-03-29sim: cr16: add _start symbol to tests [BZ #12385]Mike Frysinger2-0/+7
2015-03-29sim: microblaze: start a testsuiteMike Frysinger4-0/+55
2015-03-29sim; testsuite: allow tests to set no outputMike Frysinger2-1/+9
2015-03-29sim: testsuite: make subdir unconditionalMike Frysinger2-22/+4
2015-03-29sim: mcore: add a basic testsuiteMike Frysinger4-0/+77
2015-03-29sim: avr: fix _start testsuite symbolMike Frysinger2-1/+6
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