| Age | Commit message (Collapse) | Author | Files | Lines |
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These aren't used anymore, so punt them all.
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Now that all ports have moved to creating libsim.a in the top-level,
drop all the support code to create it in a subdir.
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The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level. This is a required step before we
can move compilation itself up, and makes it easier to review.
The downside is that each object compile is a recursive make instead of
a single one. On my 4 core system, it adds ~100msec to the build per
port, so it's not great, but it shouldn't be a big deal. This will go
away of course once the top-level compiles objects.
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This commit is the result of running the gdb/copyright.py script,
which automated the update of the copyright year range for all
source files managed by the GDB project to be updated to include
year 2023.
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These manual settings were necessary when we weren't doing automatic
header dependency tracking. That was changed a while ago, and we use
automake now to do it all for us. As a result, many of these vars
aren't even referenced anymore.
Further, some of the source file generation (e.g. .c files, or igen,
or cgen outputs) were moved to the common automake build, and it takes
care of dependency tracking for us with the object files.
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We have configure tests for this in the top-level configure script
to link this when necessary, so we don't need to explicitly list it
for specific ports.
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This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.
For the avoidance of doubt, all changes in this commits were
performed by the script.
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Use the new target-newlib-syscall module. This is needed to merge all
the architectures into a single build, and sh has a custom syscall
table for its newlib/libgloss port.
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With most of the warnings fixed in interp.c, we can enable -Werror
here too now. There are some -Wmaybe-uninitialized warnings still
lurking that look legitimate, but we don't flag those are fatal,
and I don't have the expertise to dive into each opcode to figure
out the right way to clean them up.
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These rules don't depend on the target compiler settings, so hoist
the build logic up to the common builds for better parallelization.
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Only one file in here still generates warnings, so reduce the -Werror
disable to that alone now that we require GNU make and can set variables
on a per-object basis.
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Update the gencode rules to use the silent build helpers.
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For the ports that still don't build with -Werror, rather than disable
the flag at configure time, do it at make time. This will allow us to
unify these tests in the common sim configure script.
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Some spots in the sim build used manual dependencies, and some spots
did a compilation by hand but did not use the automatic dependency
tracking code. This patch fixes these spots.
I didn't touch ppc, because it doesn't use the common Makefile code.
I also didn't touch objects that are for the build machine, because
automatic dependencies don't work for those.
sim/arm/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (armemu26.o, armemu32.o): Use COMPILE and
POSTCOMPILE.
sim/bpf/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (arch.o, cpu.o, sim-if.o, traps.o): Remove.
(mloop-le.o, mloop-be.o, decode-le.o, decode-be.o, sim-le.o)
(sim-be.o): Use COMPILE and POSTCOMPILE.
(SIM_EXTRA_DEPS): Add eng-le.h, eng-be.h.
sim/cr16/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (SIM_EXTRA_DEPS): New variable.
(simops.o): Remove.
sim/cris/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (sim-if.o, dv-cris.o, dv-rv.o, arch.o, traps.o)
(devices.o, crisv10f.o, mloopv10f.o, cpuv10.o, decodev10.o)
(modelv10.o, crisv32f.o, mloopv32f.o, cpuv32.o, decodev32.o)
(modelv32.o): Remove.
(SIM_EXTRA_DEPS): Add engv10.h.
sim/d10v/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (SIM_EXTRA_DEPS): New variable.
(simops.o): Remove.
sim/frv/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (arch.o, devices.o, frv.o, traps.o, pipeline.o)
(interrupts.o, memory.o, cache.o, options.o, reset.o)
(registers.o, profile.o, profile-fr400.o, profile-fr450.o)
(profile-fr500.o, profile-fr550.o, sim-if.o, mloop.o, cpu.o)
(decode.o, sem.o, model.o): Remove.
(SIM_EXTRA_DEPS): Add eng.h.
sim/iq2000/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (sim-if.o): Remove.
(arch.o): Use COMPILE and POSTCOMPILE.
(devices.o, iq2000.o, mloop.o, cpu.o, decode.o, sem.o, model.o):
Remove.
(SIM_EXTRA_DEPS): Add eng.h.
sim/lm32/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (arch.o, traps.o, sim-if.o, lm32.o, mloop.o)
(cpu.o, decode.o, sem.o, model.o): Remove.
(SIM_EXTRA_DEPS): Add eng.h.
sim/m32r/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (sim-if.o, arch.o, traps.o, traps-linux.o)
(devices.o, m32r.o, mloop.o, cpu.o, decode.o, sem.o, model.o)
(m32rx.o, mloopx.o, cpux.o, decodex.o, semx.o, modelx.o)
(m32r2.o, mloop2.o, cpu2.o, decode2.o, sem2.o, model2.o): Remove.
(SIM_EXTRA_DEPS): Add eng.h, engx.h, eng2.h.
sim/m68hc11/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (interp.o): Remove.
sim/mips/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
Remove.
(SIM_EXTRA_DEPS): New variable.
sim/mn10300/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (interp.o): Remove.
(idecode.o op_utils.o semantics.o): Remove.
sim/or1k/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (mloop.o, arch.o, cpu.o, decode.o, sem.o)
(sem-switch.o, model.o): Remove.
sim/rl78/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (err.o, fpu.o, gdb-if.o, load.o, main.o, mem.o)
(reg.o, rl78.o): Remove.
sim/rx/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (err.o, fpu.o, gdb-if.o, load.o, main.o, mem.o)
(misc.o, reg.o, rx.o, syscalls.o, trace.o): Remove.
sim/sh/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (SIM_EXTRA_DEPS): New variable.
(interp.o): Remove.
sim/v850/ChangeLog
2021-04-22 Tom Tromey <tom@tromey.com>
* Makefile.in (interp.o, simops.o, semantics.o): Remove.
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Rather than hand duplicate the syscall table, switch to the common
nltvals framework. We have to tweak the constant names, but we get
everything else for free. I made sure the constants have the same
values before & after too :).
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These use the same pattern as seen in the opcodes/ dir and in automake
in general (ish). This helps simplify the boilerplate for building and
linking build-time code, and fixes some inconsistency in flag usage.
For rules that were compiling+linking in a single step, split them into
separate steps so we can apply the correct set of options. This matches
automake behavior too.
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This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
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gdb/ChangeLog:
Update copyright year range in all GDB files.
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This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
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gdb/ChangeLog:
Update copyright year range in all GDB files
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This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
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gdb/ChangeLog:
Update year range in copyright notice of all files.
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Pretty much all targets are using this module already, so add it to the
common list of objects. The only oddball out here is cris and that's
because it supports loading via an offset for all the phdrs. We drop
support for that.
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Now that all arches (for the most part) have moved over, move sim-stop.o,
sim-reason.o, and sim-reg.o to the common object list and out of all the
arch ports.
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Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
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This makes these two objects available to all sims by default.
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A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
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The build line was missing the normal BUILD_xxx flags. Once we added
that, we get warnings that weren't shown before. As we fix those, we
notice that the -d option segfaults because it tries to write readonly
memory. Fix that too as part of the const/prototype clean up.
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We want people to stop using the run.c frontend, but it's hard to notice
when it's still set as the default. Lets flip things so nrun.c is the
default, and users of run.c will get an error by default. We turn that
error into a warning for existing sims so we don't break them -- this is
mostly meant for people starting new ports.
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gdb/ChangeLog:
Update year range in copyright notice of all files.
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Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
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gdb/ChangeLog:
Copyright year update in most files of the GDB Project.
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in the previous copyright update.
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to GPLv3.
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* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp,
renumbering the sh-dsp registers to use distinct numbers.
sim/sh:
* Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h.
* interp.c: Include "gdb/sim-sh.h".
(sim_store_register, sim_fetch_register): Use constants defined there.
gdb:
* sh-tdep.c (sh_dsp_register_sim_regno): New function.
(sh_gdbarch_init): Use it for sh-dsp.
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* Makefile.in (interp.o): Depends on ppi.c .
(ppi.c): New rule.
* gencode.c (printonmatch, think, genopc): Deleted.
(MAX_NR_STUFF): Now 42.
(tab): Add SH-DSP CPU instructions.
Amalgamate ldc / stc / lds / sts instructions with similar
bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>.
Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
(movsxy_tab): New array.
For movs, change MMMM field to GGGG, and mmmm field to MMMM.
Added entries for movx, movy and parallel processing insns.
(ppi_tab): New array.
(qfunc): Stabilize sort.
(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
(dumptable): Now takes three arguments. Changed all callers.
Emit just one contigous jump table.
(filltable): Now takes an argument. Changed all callers.
Make index static.
(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
(gensim_caselist): New function, broken out of gensim.
Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
Handle ref '9'.
(gensim): Handle 'N' in code field and '8' in refs field.
Call gensim_caselist - twice.
(ppi_index): New static variable.
(main): Unsupport default action.
Add dsp support for -x / -s option. Add -p option.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
(saved_state_type): Rearrange to allow amalgamated ldc / stc /
lds / sts to work efficiently.
(target_dsp): New static variable.
(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
(set_fpscr1): Likewise. Use target_dsp to check for dsp.
(MOD_MSi, SIG_BUS_FETCH): Deleted.
(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
(SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead
of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
(set_sr): Reflect saved_state_type change. Fix SR_RB handling.
Use SET_MOD.
(MA, L, TL, TB): Now controlled by ACE_FAST.
(SEXT32): Just cast to int.
(SIGN32): Fixed to only shift by 31.
(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
(ppi_insn): Declare.
(ppi.c): Include.
(init_dsp): Set target_dsp. When it changes, switch end of
sh_jump_table with sh_dsp_table.
(sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead.
Don't Declare PR if it's #defined.
Fix single-stepping (Was broken in Mar 6 16:59:10 patch).
(sim_store_register, sim_read_register): Translate accesses to
reflect saved_state_type change.
* interp.c (set_sr): Set sr.
(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
(DSP_R): Fix definition.
(sim_resume): Remove outdated SET_SR use.
* interp.c (saved_state): New members for struct member asregs:
rs, re, insn_end, xram_start, yram_start.
(struct loop_bounds): New struct.
(SKIP_INSN): New macro.
(get_loop_bounds): New function.
(endianw): Renamed to global_endianw.
(maskw): negated bits.
(PC): Now insn_ptr.
(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
(SIG_BUS_FETCH): Likewise
(raise_exception, riat_fast): New functions.
(raise_buserror, sim_stop): Use raise_exception.
(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
Reverse sense of mask argument.
(FP_OP, set_dr): Use RAISE_EXCEPTION.
(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
Declare. Remove redundant masking.
(wwat_fast, rwat_fast): Add argument endianw. Changed callers.
(MA): Updated for change pc -> PC.
(Delay_Slot): Use RIAT.
(empty): Deleted.
(trap): Remove argument little_endian. Add argument endianw.
Changed all callers. Use raise_exception.
(macw): Add argument endainw. Changed all callers.
(init_dsp): New function, extended after broken out of init_pointers.
(sim_resume): Replace pc with insn_ptr. Replace little_endian with
endianw. Replace nia with nip. Reverse sense of maskb / maskw /
maskl. Implement logic for zero-overhead loops. Don't try to
interpret garbage when getting a SIGBUS at insn fetch.
(sim_open): Call init_dsp.
* gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H /
RAISE_EXCEPTION where appropriate.
Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.
* interp.c (sim_store_register, sim_fetch_register):
Do proper endianness switch.
* interp.c (saved_state_type): New members for struct member asregs:
xymem_select, xmem, ymem, xmem_offset, ymem_offset.
(special_address): Delete.
(BUSERROR): Now a two-argument predicate.
(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
(process_wlat_addr, process_wwat_addr): New functions.
(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
(process_rbat_addr): Likewise.
(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
(do_rdat, trap): Delete SLOW code.
(SEXT32, SIGN32): New macros.
(swap, swap16): Now integer in - integer out. Changed all callers.
(strswaplen, strnswap): Delete SLOW versions.
(init_pointers): Initialize dsp memory selection (preliminary).
(sim_store_register, sim_fetch_register): Use swap instead of
big / little endian read / write functions.
* interp.c (maskl): Deleted.
(endianw, endianb): New variables.
(special_address): Now inline.
(bp_holder): Put raising of buserror there, rename to:
(raise_buserror).
(BUSERROR): Now yields a value. Changed all users.
(wbat_big): Delete.
(wlat_fast, wwat_fast, wbat_fast): New functions.
(rlat_fast, rwat_fast, rbat_fast): Likewise.
(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
(do_rdat, do_wdat): Likewise. Take maskl argument instead of
little_endian one. Changed caller macros.
(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
(strswaplen, strnswap): New functions.
(trap): Use them to fix up endian mismatches;
disable SYS_execve and SYS_execv; fix double address translation for
SYS_pipe and SYS_stat.
(sym_write, sym_read): Add endianness translation.
(sym_store_register, sym_fetch_register): Add maskl local variable.
(sim_open): Set endianw and endianb.
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* interp.c (target_byte_order): Delete.
(sim_kind, myname, little_endian_p): New static locals.
(init_pointers): Use little_endian_p instead of target_byte_order.
(sim_resume): Likewise.
(sim_open): Set sim_kind, myname. Set little_endian_p from -E arg.
(sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
load file into simulator. Set start address from bfd.
(sim_create_inferior): Return SIM_RC. Delete arg start_address.
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scheme which is more compatible with WinGDB builds.
* configure.in: Improve comment on how to run autoconf.
* configure: Re-run autoconf to get new ../common/aclocal.m4.
* Makefile.in: Use autoconf substitution to install common
makefile fragment.
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* configure: Rebuild.
* Makefile.in (INSTALL): Revert to using install.sh.
(INSTALL_PROGRAM, INSTALL_DATA): Set to $(INSTALL).
(INSTALL_XFORM, INSTALL_XFORM1): Restore.
(CC_FOR_BUILD): Restore.
(gencode): Build using $(CC_FOR_BUILD).
(install): Don't install in $(tooldir).
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* run.c: Don't include sysdep.h.
* Makefile.in (INSTALL{,_PROGRAM,_DATA}): Use autoconf computed value.
(CC, CFLAGS, AR, RANLIB): Likewise.
(HDEFINES, TDEFINES): Define.
(CC_FOR_BUILD): Delete.
(host_makefile_frag): Delete.
(Makefile): Don't depend on frags.
* configure.in (sysdep.h): Don't create symlink.
(host_makefile_frag, frags): Deleted.
(CC, CFLAGS, AR, RANLIB, INSTALL): Compute values.
* configure: Regenerated.
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* configure: New file, generated with autconf 2.4.
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