riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2023-01-11	sim: build: drop subdir Makefile.in files	Mike Frysinger	1	-22/+0
	These aren't used anymore, so punt them all.
2023-01-10	sim: build: drop support for creating libsim.a in subdirs	Mike Frysinger	1	-2/+0
	Now that all ports have moved to creating libsim.a in the top-level, drop all the support code to create it in a subdir.
2023-01-10	sim: riscv: move libsim.a creation to top-level	Mike Frysinger	1	-6/+1
	The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects.
2023-01-01	Update copyright year range in header of all files managed by GDB	Joel Brobecker	1	-1/+1
	This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
2022-11-07	sim: riscv: drop subdir configure logic	Mike Frysinger	1	-0/+2
	We've been using this only to set the default word size to 32-vs-64 based on the $target. We can easily merge this with the top-level configure script to clean things up a bit.
2022-01-01	Automatic Copyright Year update after running gdb/copyright.py	Joel Brobecker	1	-1/+1
	This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
2021-11-28	sim: riscv: switch to new target-newlib-syscall	Mike Frysinger	1	-3/+0
	Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and riscv has a custom syscall table for its newlib/libgloss port.
2021-02-04	sim: riscv: new port	Mike Frysinger	1	-0/+30
	This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.