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2004-06-262000-08-07 Graham Stott <grahams@cygnus.co.uk>Alexandre Oliva7-1/+3727
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo. 2000-05-29 Alexandre Oliva <aoliva@cygnus.com> * interp.c (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Take additional state arguments. Print exception type and call program_interrupt. Adjust callers. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional arguments. * mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Adjust prototypes. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise. * am33-2.igen: Adjust calls. 2000-05-19 Alexandre Oliva <aoliva@cygnus.com> * op_utils.c (cmp2fcc): Moved... * interp.c: ... here. 2000-05-18 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant. 2000-05-15 Alexandre Oliva <aoliva@cygnus.com> * mn10300_sim.h: Include sim-fpu.h. (FD2FPU, FPU2FD): Enclose the FD argument in parentheses. (fpu_check_signal_exception): Declare. (struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise. (FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare. * interp.c (fpu_disabled_exception): Document. (fpu_unimp_exception): Likewise. (fpu_check_signal_exception): Define. (reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise. (reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise. (REG2VAL, ROUND, VAL2REG): Define shorthands. (fpu_status_ok): Define. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define. * am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv, fmadd, fmsub, fnmadd, fnmsub): Use new functions. 2000-04-27 Alexandre Oliva <aoliva@cygnus.com> * interp.c (sim_create_inferior): Set PSW bit to enable FP insns if architecture is AM33/2.0. * am33.igen: Include am33-2.igen. 2000-04-23 Alexandre Oliva <aoliva@cygnus.com> * mn10300.igen (movm, call, ret, retf): Check for am33_2 too. * am33.igen (movm): Likewise. 2000-04-19 Alexandre Oliva <aoliva@cygnus.com> * am33.igen: Added `*am33_2' to some instructions that were missing it. 2000-04-07 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: New file. All insns implemented, but FP flags are only set for fcmp, exceptional conditions are not handled yet. * Makefile.in (IGEN_INSN): Added am33-2.igen. (tmp-igen): Added -M am33_2. * mn10300.igen, am33.igen: Added `*am33_2' to all insns. * gencode.c: Support FMT_D3. * mn10300_sim.h (dword): New type. (struct _state): Added fpregs. (REG_FPCR, FPCR): New define. All assorted bitmaps. (XS2FS, AS2FS, Xf2FD): New macros. (FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise. (load_dword, store_dword): New functions or macros. (u642dw, dw2u64): New functions. (fpu_disabled_exception, fpu_unimp_exception): Declared. * interp.c (fpu_disabled_exception): Defined; no actual implementation. (fpu_unimp_exception): Likewise. * op_utils.c (cmp2fcc): New function.
2004-06-26* interp.c, mn10300_sim.h, op_utils.c: Convert function prototypesAlexandre Oliva4-81/+66
and definitions to ISO C.
2004-06-26* gencode.c, simops.c: Delete.Alexandre Oliva4-3433/+6
* Makefile.in: Remove non-COMMON dependencies and commands.
2004-06-26* configure.in: Use common simulator always. Don't subst sim_genAlexandre Oliva5-1080/+19
nor mn10300_common. * configure: Rebuilt. * Makefile.in (WITHOUT_COMMON_OBJS, WITHOUT_COMMON_INTERP_DEP, WITHOUT_COMMON_RUN_OBJS): Remove. (WITH_COMMON_OBJS): Rename to MN10300_OBJS. (WITH_COMMON_INTERP_DEP): Rename to MN10300_INTERP_DEP. (WITH_COMMON_RUN_OBJS): Rename to SIM_RUN_OBJS. (SIM_EXTRA_CFLAGS): Don't use @sim_gen@. * interp.c: Remove non-common bits. * mn10300_sim.h: Likewise.
2003-08-28Index: common/ChangeLogAndrew Cagney3-8/+18
2003-08-28 Andrew Cagney <cagney@redhat.com> * dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof. * sim-options.c (print_help): Cast the format with specifier to "int". Index: mn10300/ChangeLog 2003-08-28 Andrew Cagney <cagney@redhat.com> * dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to "long". (read_status_reg): Cast "serial_reg" to "long". * dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to "long". (do_counter6_event, write_mode_reg, write_tm6md): Ditto.
2003-02-27Index: arm/ChangeLogAndrew Cagney2-4/+9
2003-02-27 Andrew Cagney <cagney@redhat.com> * wrapper.c (sim_create_inferior, sim_open): Rename _bfd to bfd. Index: common/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-utils.h (sim_analyze_program, sim_load_file): Rename _bfd to bfd. * sim-hload.c (sim_load), sim-base.h (sim_state_base): Ditto. * nrun.c (main): Ditto. Index: d10v/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: erc32/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interf.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8500/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: i960/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m32r/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m68hc11/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_prepare_for_program, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: mcore/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mips/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open): (sim_create_inferior): Index: mn10200/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mn10300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: ppc/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim_calls.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: sh/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd to bfd. Index: v850/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: z8k/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * iface.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
2003-02-26Index: common/ChangeLogAndrew Cagney2-1/+5
2003-02-26 Andrew Cagney <cagney@redhat.com> * sim-engine.h (sim_engine_abort): Add noreturn attribute. (sim_engine_vabort): Ditto. (sim_engine_halt, sim_engine_restart): Ditto. Index: mn10300/ChangeLog 2003-02-26 Andrew Cagney <cagney@redhat.com> * am33.igen: Call sim_engine_abort instead of abort.
2003-02-262003-02-26 David Carlton <carlton@math.stanford.edu>David Carlton2-1/+10
* dv-mn103tim.c (read_special_timer6_reg): Add break after empty default: label. (write_special_timer6_reg): Ditto. Update copyright.
2002-11-282002-11-28 Andrew Cagney <cagney@redhat.com>Andrew Cagney3-1/+7
* sim-main.h: Only include "idecode.h" once. * Makefile.in (SIM_EXTRA_DEPS): Define.
2002-06-16Import current --enable-gdb-build-warnings.Andrew Cagney2-167/+220
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney4-5/+11
Update accordingly.
2001-05-07*** empty log message ***Jim Blandy1-0/+4
2001-05-07* mn10300.igen: Doc fixes.Jim Blandy1-6/+6
2001-04-26* Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o):Alexandre Oliva2-2/+7
Depend on targ-vals.h.
2001-04-15* Makefile.in (simops.o): Add simops.h to dependency list.J.T. Conklin2-1/+5
2000-08-09* am33.igen: Warning clean-up.Alexandre Oliva2-42/+24
(movm): Initialize PC and mask. (mov, movbu, movhu): Set srcreg2 from RI0. (bsch): Initialize c. (sat16_cmp): Actually do the comparison. (mov_llt): Do not overwrite dstreg with uninitialized variable.
2000-05-29minor formatting tweaks to aid syncronisationNick Clifton2-8/+17
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2-157/+172
2000-05-22* am33.igen: Fix leading comments of SP-relative offset insns thatAlexandre Oliva2-7/+11
referred to other registers. Make their offsets unsigned.
2000-05-18* mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,Alexandre Oliva5-167/+175
genericXor, genericBtst): Use `unsigned32'. * op_utils.c: Likewise. * mn10300.igen, am33.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant.
2000-04-25* am33.igen (inc4 Rn): Use genericAdd so as to modify flags.Alexandre Oliva2-1/+5
2000-04-09* am33.igen: Make SP-relative offsets unsigned. Add `*am33' forAlexandre Oliva2-11/+34
some instructions that were missing it.
2000-03-03* build fixFrank Ch. Eigler2-2/+6
2000-03-03 Alexandre Oliva <oliva@lsd.ic.unicamp.br> * Makefile.in (IGEN_INSN): Added am33.igen.
1999-12-07import gdb-1999-12-06 snapshotJason Molenda5-0/+9574
1999-09-09import gdb-1999-09-08 snapshotStan Shebs2-168/+176
1999-07-19import gdb-1999-07-19 snapshotJason Molenda2-4/+8
1999-05-11import gdb-1999-05-10Stan Shebs2-184/+318
1999-04-26import gdb-19990422 snapshotStan Shebs6-7/+60
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs21-0/+18250
1999-04-16Initial creation of sourceware repositoryStan Shebs21-26548/+0
1999-01-26am33 is now kept with --keep-cygnus.Jeff Law1-11/+11
1999-01-07* Removing last known memories of tx3904 and am30 sanitization.Frank Ch. Eigler1-34/+5
1998-12-30* eCos->devo merge; am30 sanitization tags removedFrank Ch. Eigler3-115/+255
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o. * interp.c (sim_open): Add stub mn103002 cache control memory regions. Set OPERATING_ENVIRONMENT on "stdeval1" board. (mn10300_core_signal): New function to intercept memory errors. (program_interrupt): New function to dispatch to exception vector (mn10300_exception_*): New functions to snapshot pre/post exception state. * sim-main.h (SIM_CORE_SIGNAL): Define hook - call mn10300_core_signal. (SIM_ENGINE_HALT_HOOK): Do nothing. (SIM_CPU_EXCEPTION*): Define hooks to call mn10300_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * dv-mn103ser.c (*): Support dv-sockser backend for UART I/O. Various endianness and warning fixes. * mn10300.igen (illegal): Call program_interrupt on error. (break): Call program_interrupt on breakpoint Several changes from <janczyn@cygnus.com> and <cagney@cygnus.com> merged in: * dv-mn103int.c (mn103int_ioctl): New function for NMI generation. (mn103int_finish): Install it as ioctl handler. * dv-mn103tim.c: Support timer 6 specially. Endianness fixes.
1998-08-26Regress yesterday's change to jmp instn implementation in mn10300.igen.Joyce Janczyn1-5/+0
1998-08-26Regress yesterday's change to jmp instruction -- it has deceiving syntax.Joyce Janczyn2-17/+32
Also tidy up some code to match documentation and fix div, divu by 0.
1998-08-25* mn10300.igen (OP_F0F4): Need to load contents of register AN0Joyce Janczyn2-277/+287
for jmp.
1998-08-24* sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA.Joyce Janczyn1-0/+14
1998-07-27 * am33.igen: Detect cases where two operands must not match inJeff Law2-38/+49
non-DSP instructions.
1998-07-24Fri Jul 24 18:15:21 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+10
* op_utils.c (do_syscall): Rewrite to use common/syscall.c. (syscall_read_mem, syscall_write_mem): New functions for syscall callbacks. * mn10300_sim.h: Add prototypes for syscall_read_mem and syscall_write_mem. * mn10300.igen: Change C++ style comments to C style comments. Check for divide by zero in div and divu ops.
1998-07-24 * am33.igen (translate_xreg): New function. Use it as needed.Jeff Law2-28/+39
1998-07-23 * am33.igen: Add some missing instructions.Jeff Law2-11/+240
Missed a few last week... Grrr.
1998-07-23 * am33.igen: Autoincrement loads/store fixes.Jeff Law2-34/+259
1998-07-21 * am33.igen: Add most am33 DSP instructions.Jeff Law2-15/+3540
1998-07-14Fix goof.Jeff Law1-3/+3
1998-07-09 * am33.igen: Fix Z bit for remaining addc/subc instructions.Jeff Law2-40/+53
Do not sign extend immediate for mov imm,XRn. More random mul, mac & div fixes. Remove some unused variables. Sign extend 24bit displacement in memory addresses. Whee, more fixes.
1998-07-09 * mn10300.igen: Fix Z bit for addc and subc instructions.Jeff Law2-21/+36
Minor fixes in multiply/divide patterns. start-sanitize-am33 * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various fixes to 2 register multiply, divide and mac instructions. Set Z,N correctly for sat16. Sign extend 24 bit immediate for add, and sub instructions. * am33.igen: Add remaining non-DSP instructions. end-sanitize-am33
1998-07-09 * am33.igen: Add remaining non-DSP instructions.Jeff Law2-20/+690
Lots of work still remains. PSW handing is probably broken badly and the mul/mac classes of instructions are probably not handled correctly.
1998-07-09 * am33.igen (translate_rreg): New function. Use it as appropriate.Jeff Law2-2335/+374
1998-07-08 * am33.igen: More am33 instructions. Fix "div".Jeff Law2-88/+1626
1998-07-06 * mn10300.igen: Add am33 support.Jeff Law2-446/+1365
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